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RT3606BC ? ds3606bc-04 june 2016 www.richtek.com 1 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. simplified application circuit dual channel pwm controller with integrated driver for imvp8 cpu core power supply general description the RT3606BC is an imv p8 compliant cpu power controller which includes two voltage rails : a 3/2/1 phase synchronous buck controller, the core vr and a 2/1 phase synchronous buck controller, the axg vr. the RT3606BC adopts g-navp tm (green native avp) which is richtek ' s proprietary topology derived from finite dc gain of ea amplifier with current mode control, making it easy to set the droop to meet all intel cpu requirements of avp (adaptive voltage positioning). based on the g- navp tm topology, the RT3606BC also features a quick response mechanism for optimized avp performance during load transient. the RT3606BC supports mode transition function with various operating states. a serial vid (svid) interface is built in the RT3606BC to communicate with intel imvp8 compliant cpu. the RT3606BC supports vid on-the-fly function with three different slew rates : fast, slow and decay. by utilizing the g-navp tm topology, the operating frequency of the RT3606BC varies with vid, load and input voltage to further enhance the efficiency even in ccm. moreover, the g- navp tm with ccrcot (constant current ripple cot) technology provides superior output voltage ripple over the entire input/output range. the built-in high accuracy dac converts the svid code ranging from 0.25v to 1.52v with 5mv per step. the RT3606BC integrates a high accuracy adc for platform setting functions, such as quick response trigger level or over-current level. besides, the setting function also supports this two rails address exchange. the RT3606BC provides vr ready output signals. it also features complete fault protection functions including over-voltage (ov), negative voltage (nv), over- current (oc) and under-voltage lockout (uvlo). the RT3606BC is available in the wqfn-60l 7x7 small foot print package. features ? ? ? ? ? intel imvp8 serial vid interface compatible power management states ? ? ? ? ? 3/2/1 phase (core vr) + 2/1 phase (axg vr) pwm controller ? ? ? ? ? 2 embedded mosfet drivers at the core vr, 1 embedded mosfet driver at the axg vr ? ? ? ? ? g-navp tm (green native adaptive voltage positioning) topology ? ? ? ? ? 0.5% dac accuracy ? ? ? ? ? differential remote voltage sensing ? ? ? ? ? built-in adc for platform programming ? ? ? ? ? accurate current balance ? ? ? ? ? system thermal compensated avp ? ? ? ? ? diode emulation mode at light load condition for single phase operation ? ? ? ? ? fast transient response ? ? ? ? ? vr ready indicator ? ? ? ? ? thermal throttling ? ? ? ? ? current monitor output ? ? ? ? ? ovp, ocp, nvp, uvlo ? ? ? ? ? slew rate setting/address flip function ? ? ? ? ? rail address flexibility ? ? ? ? ? dvid enhancement applications ? imvp8 intel core supply ? notebook/ desktop computer/ servers multi-phase cpu core supply ? avp step-down converter RT3606BC v axg pwma2 driver mosfet v core phase1 phase2 mosfet mosfet pwm3 driver mosfet phasea1 mosfet pgood vclk vdio vr_hot alert to pch to cpu
2 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wqfn-60l 7x7 marking information RT3606BCgqw : product number ymdnn : date code pin no pin name pin function 1 pwm3 pwm output for core rail vr of channel 3. 2 pgood vr ready indicator. 3 tonset core rail vr on-time setting. an on-time setting resistor is connected from this pin to input voltage. 4 tsen thermal sense input for core rail vr. 8, 9, 5 isen[1:3]p positive current sense inputs of multi-phase core rail vr channel 1, 2 and 3. 7, 10, 6 isen[1:3]n negative current sense inputs of multi-phase core rail vr channel 1, 2 and 3. 11 fb negative input of the error amplifier. this pin is for core rail vr output voltage feedback to controller. 12 comp core rail vr compensation. this pin is the error amplifier output pin. 13 vsen core rail vr voltage sense input. this pin is connected to the terminal of core rail vr output voltage. 14 rgnd return ground for core rail vr. this pin is the negative node of the differential remote voltage sensing. 15 set1 1 st platform setting. platform can use this pin to set ocs, dvid threshold and iccmax for core rail vr. 16 set2 2 nd platform setting. platform can use this pin to set rset, qrth, qrwidth and dvid width for core rail vr. moreover, set2 pin features a special function for users to confirm the soldering condition of the controller under zero vboot condition. connect the set2 pin to 5v and turn on the en pin, if the soldering is good, both rails will output 0.8v. package type qw : wqfn-60l 7x7 (w-type) RT3606BC lead plating system g : green (halogen free and pb free) RT3606BC gqw ymdnn pwm3 tsen tonset comp fb isen2n isen2p isen1p isen1n isen3p isen3n pgood set2 set3 seta1 seta2 imon vcc imona vdio vclk ps4_dr tsena tonseta compa fba isena2n isena2p nc isena1n isena1p dvd ugate1 phase1 lgate1 boot2 ugate2 ugatea1 phase2 lgate2 pvcc lgatea1 vsena rgnda ibias ofsm ofsa/psys vsen rgnd boota1 pwma2 boot1 phasea1 vref set1 nc en nc gnd 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 51 52 53 54 55 56 57 58 59 60 46 47 48 49 50 27 26 25 24 23 22 21 20 19 18 17 16 30 29 28 vr_hot alert
3 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no pin name pin function 17 set3 3 rd platform setting. platform can use this pin to set vr address, zero load-line, anti- overshoot function and behavior, ai gain, disable dvid compensation, decrease gtu and sa ramp (only in maximum phase = 1-phase), high frequency ramp, dvid slew rate, and psys function for core vr and axg vr. 18 seta1 1 st platform setting. platform can use this pin to set ocs, dvid threshold and iccmax for axg rail vr. 19 seta2 2nd platform setting. platform can use this pin to set rset, qrth, qrwidth and dvid width for axg rail vr. 20 imon core rail vr current monitor output. this pin outputs a voltage proportional to the loading current. 21 vref fixed 0.6v output reference voltage. this voltage is only used to offset the output voltage of imon pin. between this pin and gnd must be placed a rc circuit with r = 1 ? and c = 0.47 ? f. 22 imona axg rail vr current monitor output. this pin outputs a voltage proportional to the loading current. 23 vr_hot thermal monitor output, this pin is active low. 24 alert svid alert. (active low) 25 vdio vr and cpu data transmission interface. 26 vclk synchronous clock from the cpu. 27 en vr enable control input. 28 ofsm output voltage offset setting for core rail vr. 29 ofsa/psys output voltage offset setting for axg rail vr / system input power monitor. place the psys resistor as close to the ic as possible. 30 vcc controller power supply. connect this pin to 5v and place a decoupling capacitor 2.2 ? f at least. the decoupling capacitor is placed as close vr controller as possible. 31, 39, 46 nc no internal connection. 32 ibias internal bias current setting. connect a 100k ? resistor from this pin tied to gnd to set the internal current. don?t connect a bypass pass capacitor from this pin to gnd. 33 rgnda return ground for axg rail vr. this pin is the negative node of the differential remote voltage sensing. 34 vsena axg rail vr voltage sense input. this pin is connected to the terminal of axg rail vr output voltage. 35 compa axg rail vr compensation. this pin is the error amplifier output pin. 36 fba negative input of the error amplifier. this pin is for axg rail vr output voltage feedback to controller. 40, 38 isena[1:2]p positive current sense input of multi-phase axg rail vr channel 1, 2. 41, 37 isena[1:2]n negative current sense input of multi-phase axg rail vr channel 1, 2. 42 tsena thermal sense input for axg rail vr. 43 tonseta axg rail vr on-time setting. an on-time setting resistor is connected from this pin to input voltage. 44 dvd divided input voltage detection of power stage. connect this pin to a voltage divider from input voltage of power stage to detect input voltage.
4 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no pin name pin function 45 ps4_dr dr.mos enable control. connecting to dr.mos ps4 function pin. as received ps4 command, this pin will be floating. if the dr. mos needs active low to enter ps4 or use discrete mosfet, please reserve a 100k resistor to gnd. 47 pwma2 pwm output for axg rail vr channel 2. 48 boota1 bootstrap supply for high-side gate mosfet driver for axg rail vr. 49 ugatea1 high-side drive outputs for axg rail vr. connect the pin to the gate of high-side mosfet. 50 phasea1 switch node of high-side driver for axg rail vr. connect the pin to high-side mosfe source together with the low-side mosfet drain and inductor. 51 lgatea1 low-side driver output for axg rail vr. this pin drives the gate of low-side mosfet. 52 pvcc driver power supply input. connect this pin to gnd by a minimum 2.2 ? f ceramic capacitor. 57, 53 lgate[1:2] low-side driver output for core rail vr. this pin drives the gate of low-side mosfet. 58, 54 phase[1:2] switch node of high-side driver for core rail vr. connect the pin to high-side mosfe source together with the low-side mosfet drain and inductor. 59, 55 ugate[1:2] high-side drive outputs for core rail vr. connect the pin to the gate of high-side mosfet. 60, 56 boot[1:2] bootstrap supply for high-side gate mosfet driver for core rail vr. 61 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
5 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram loop control protection logic svid interface configuration registers control logic uvlo vref gnd fb comp rgnd ugate1 soft-start & slew rate control vset_m error amp from control logic offset cancellation isen3n isen3p isen2n isen2p isen1n isen1p current balance + - + - dac ton gen + - + - + - current mirror ic1_m current mirror current mirror + - ocs_m imon pwm cmp + - + rset_m tonset imon filter imoni_m 1/3 dvid sr dvidth_m dvidwidth_m ib1_m ic2_m ib2_m ic3_m ib3_m gm v ref ocs_th_m qrth_m qrwidth_m ib1_m ib2_m ib3_m ps_m boot1 pvcc pwm3 fba compa rgnda soft-start & slew rate control vset_a error amp from control logic offset cancellation isena2n isena2p isena1n isena1p current balance + - + - dac ton gen + - + - current mirror ic1_a current mirror + - ocs_a imona pwm cmp + - + rset_a tonseta imon filter imoni_a 1/3 dvid sr dvidth_a dvidwidth_a ib1_a ic2_a ib2_a gm v refi ocs_th_a qrth_a qrwidth_a ib1_a ib2_a ps_a pwma2 + - vsenm vcc vdio vclk pgood en set1 set3 tsen set2 dvd ov_x/nv_x/ oc_per_x/oc_sum_x ic1_m ic2_m ic3_m ic4_m ic1_a ic2_a ic3_a ocs_m ocs_a vsena tsena seta1 ps4_dr ps_m ps_a vid_m vid_a adc imoni_a mux adc imoni_m mux dac dvidth_x dvidwidth_x qr_x qrwidth_x ocs_th_x rset_x iccmax_x ocp_per_x + - current mirror ibiasi 2v ibias seta2 vr_hot alert ofsm ofsa/psys driver boot2 lgate1 phase1 lgate2 phase2 ugate2 phasea1 ugatea1 boota1 lgatea1 pwm1 pwm2 pwma1 vr address h/l f sw ramp dvid sr disable dvid compensation decrease gtv/sa ramp (only in 1-phase) zero load-line anti-ovs anti-ovs behavior ai gain psys function anti-ovs behavior anti-ovs
6 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the RT3606BC adopts g-navp tm (green native avp) which is richtek ' s proprietary topology derived from finite dc gain of ea amplifier with current mode control, making it easy to set the droop to meet all intel cpu requirements of avp (adaptive voltage positioning). the g-navp tm controller is one type of current mode constant on-time control with dc offset cancellation. the approach can not only improve dc offset problem for increasing system accuracy but also provide fast transient response. when current feedback signal reaches comp signal, the RT3606BC generates an on-time width to achieve pwm modulation. ton gen/driver interface generate the pwm1 to pwm3 sequentially according to the phase control signal from the loop control/protection logic. pulse width is determined by current balance result and tonset pin setting. once quick response mechanism is triggered, vr will allow all pwm to turn on at the same time. pwm status is also controlled by protection logic. different protections may cause different pwm status (both high-z or lg turn-on). svid interface/configuration registers/control logic the interface receives the svid signal from cpu and sends the relative signals to loop control/protection logic for loop control to execute the action by cpu. the registers save the pin setting data from adc output. the control logic controls the adc timing and generates the digital code of the vid for vsen voltage. loop control/protection logic it controls the power on sequence, the protection behavior, and the operational phase number. mux and adc the mux supports the inputs from set1, set2, set3, seta1, seta2, imoni_m, imoni_a, tsen or tsena. the adc converts these analog signals to digital codes for reporting or performance adjustment. current balance each phase current sense signal is sent to the current balance circuit which adjusts the on-time of each phase to optimize current sharing. offset cancellation cancel the current/voltage ripple issue to get the accurate vsen. uvlo detect the dvd and vcc voltage and issue por signal as they are high enough. dac generate an analog signal according to the digital code generated by control logic. soft-start & slew rate control control the dynamic vid slew rate of dac according to the setvid fast or setvid slow. error amp error amplifier generates comp/compa signal by the difference between vsen/vsena and fb/fba. rset/rseta the ramp generator is designed to improve noise immunity and reduce jitter. pwm cmp the pwm comparator compares comp signal and current feedback signal to generate a signal for ton trigger. imon filter imon filter is used to average sum current signal by analog rc filter.
7 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. imvp8 vid code table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 0 0 0 0 0 0 1 01 0.25 0 0 0 0 0 0 1 0 02 0.255 0 0 0 0 0 0 1 1 03 0.26 0 0 0 0 0 1 0 0 04 0.265 0 0 0 0 0 1 0 1 05 0.27 0 0 0 0 0 1 1 0 06 0.275 0 0 0 0 0 1 1 1 07 0.28 0 0 0 0 1 0 0 0 08 0.285 0 0 0 0 1 0 0 1 09 0.29 0 0 0 0 1 0 1 0 0a 0.295 0 0 0 0 1 0 1 1 0b 0.3 0 0 0 0 1 1 0 0 0c 0.305 0 0 0 0 1 1 0 1 0d 0.31 0 0 0 0 1 1 1 0 0e 0.315 0 0 0 0 1 1 1 1 0f 0.32 0 0 0 1 0 0 0 0 10 0.325 0 0 0 1 0 0 0 1 11 0 .33 0 0 0 1 0 0 1 0 12 0.335 0 0 0 1 0 0 1 1 13 0.34 0 0 0 1 0 1 0 0 14 0.345 0 0 0 1 0 1 0 1 15 0.35 0 0 0 1 0 1 1 0 16 0.355 0 0 0 1 0 1 1 1 17 0.36 0 0 0 1 1 0 0 0 18 0.365 0 0 0 1 1 0 0 1 19 0.37 0 0 0 1 1 0 1 0 1a 0.375 0 0 0 1 1 0 1 1 1b 0.38 0 0 0 1 1 1 0 0 1c 0.385 0 0 0 1 1 1 0 1 1d 0.39 0 0 0 1 1 1 1 0 1e 0.395 0 0 0 1 1 1 1 1 1f 0.4 0 0 1 0 0 0 0 0 20 0.405 0 0 1 0 0 0 0 1 21 0.41 0 0 1 0 0 0 1 0 22 0.415 0 0 1 0 0 0 1 1 23 0.42 0 0 1 0 0 1 0 0 24 0.425
8 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 0 1 0 0 1 0 1 25 0.43 0 0 1 0 0 1 1 0 26 0.435 0 0 1 0 0 1 1 1 27 0.44 0 0 1 0 1 0 0 0 28 0.445 0 0 1 0 1 0 0 1 29 0.45 0 0 1 0 1 0 1 0 2a 0.455 0 0 1 0 1 0 1 1 2b 0.46 0 0 1 0 1 1 0 0 2c 0.465 0 0 1 0 1 1 0 1 2d 0.47 0 0 1 0 1 1 1 0 2e 0.475 0 0 1 0 1 1 1 1 2f 0.48 0 0 1 1 0 0 0 0 30 0.485 0 0 1 1 0 0 0 1 31 0.49 0 0 1 1 0 0 1 0 32 0.495 0 0 1 1 0 0 1 1 33 0.5 0 0 1 1 0 1 0 0 34 0.505 0 0 1 1 0 1 0 1 35 0.51 0 0 1 1 0 1 1 0 36 0.515 0 0 1 1 0 1 1 1 37 0.52 0 0 1 1 1 0 0 0 38 0.525 0 0 1 1 1 0 0 1 39 0.53 0 0 1 1 1 0 1 0 3a 0.535 0 0 1 1 1 0 1 1 3b 0.54 0 0 1 1 1 1 0 0 3c 0.545 0 0 1 1 1 1 0 1 3d 0.55 0 0 1 1 1 1 1 0 3e 0.555 0 0 1 1 1 1 1 1 3f 0.56 0 1 0 0 0 0 0 0 40 0.565 0 1 0 0 0 0 0 1 41 0.57 0 1 0 0 0 0 1 0 42 0.575 0 1 0 0 0 0 1 1 43 0.58 0 1 0 0 0 1 0 0 44 0.585 0 1 0 0 0 1 0 1 45 0.59 0 1 0 0 0 1 1 0 46 0.595 0 1 0 0 0 1 1 1 47 0.6 0 1 0 0 1 0 0 0 48 0.605 0 1 0 0 1 0 0 1 49 0.61
9 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 1 0 0 1 0 1 0 4a 0.615 0 1 0 0 1 0 1 1 4b 0.62 0 1 0 0 1 1 0 0 4c 0.625 0 1 0 0 1 1 0 1 4d 0.63 0 1 0 0 1 1 1 0 4e 0.635 0 1 0 0 1 1 1 1 4f 0.64 0 1 0 1 0 0 0 0 50 0.645 0 1 0 1 0 0 0 1 51 0.65 0 1 0 1 0 0 1 0 52 0.655 0 1 0 1 0 0 1 1 53 0.66 0 1 0 1 0 1 0 0 54 0.665 0 1 0 1 0 1 0 1 55 0.67 0 1 0 1 0 1 1 0 56 0.675 0 1 0 1 0 1 1 1 57 0.68 0 1 0 1 1 0 0 0 58 0.685 0 1 0 1 1 0 0 1 59 0.69 0 1 0 1 1 0 1 0 5a 0.695 0 1 0 1 1 0 1 1 5b 0.7 0 1 0 1 1 1 0 0 5c 0.705 0 1 0 1 1 1 0 1 5d 0.71 0 1 0 1 1 1 1 0 5e 0.715 0 1 0 1 1 1 1 1 5f 0.72 0 1 1 0 0 0 0 0 60 0.725 0 1 1 0 0 0 0 1 61 0.73 0 1 1 0 0 0 1 0 62 0.735 0 1 1 0 0 0 1 1 63 0.74 0 1 1 0 0 1 0 0 64 0.745 0 1 1 0 0 1 0 1 65 0.75 0 1 1 0 0 1 1 0 66 0.755 0 1 1 0 0 1 1 1 67 0.76 0 1 1 0 1 0 0 0 68 0.765 0 1 1 0 1 0 0 1 69 0.77 0 1 1 0 1 0 1 0 6a 0.775 0 1 1 0 1 0 1 1 6b 0.78 0 1 1 0 1 1 0 0 6c 0.785 0 1 1 0 1 1 0 1 6d 0.79 0 1 1 0 1 1 1 0 6e 0.795
10 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 0 1 1 0 1 1 1 1 6f 0.8 0 1 1 1 0 0 0 0 70 0.805 0 1 1 1 0 0 0 1 71 0.81 0 1 1 1 0 0 1 0 72 0.815 0 1 1 1 0 0 1 1 73 0.82 0 1 1 1 0 1 0 0 74 0.825 0 1 1 1 0 1 0 1 75 0.83 0 1 1 1 0 1 1 0 76 0.835 0 1 1 1 0 1 1 1 77 0.84 0 1 1 1 1 0 0 0 78 0.845 0 1 1 1 1 0 0 1 79 0.85 0 1 1 1 1 0 1 0 7a 0.855 0 1 1 1 1 0 1 1 7b 0.86 0 1 1 1 1 1 0 0 7c 0.865 0 1 1 1 1 1 0 1 7d 0.87 0 1 1 1 1 1 1 0 7e 0.875 0 1 1 1 1 1 1 1 7f 0.88 1 0 0 0 0 0 0 0 80 0.885 1 0 0 0 0 0 0 1 81 0.89 1 0 0 0 0 0 1 0 82 0.895 1 0 0 0 0 0 1 1 83 0.9 1 0 0 0 0 1 0 0 84 0.905 1 0 0 0 0 1 0 1 85 0.91 1 0 0 0 0 1 1 0 86 0.915 1 0 0 0 0 1 1 1 87 0.92 1 0 0 0 1 0 0 0 88 0.925 1 0 0 0 1 0 0 1 89 0.93 1 0 0 0 1 0 1 0 8a 0.935 1 0 0 0 1 0 1 1 8b 0.94 1 0 0 0 1 1 0 0 8c 0.945 1 0 0 0 1 1 0 1 8d 0.95 1 0 0 0 1 1 1 0 8e 0.955 1 0 0 0 1 1 1 1 8f 0.96 1 0 0 1 0 0 0 0 90 0.965 1 0 0 1 0 0 0 1 91 0.97 1 0 0 1 0 0 1 0 92 0.975 1 0 0 1 0 0 1 1 93 0.98
11 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 0 0 1 0 1 0 0 94 0.985 1 0 0 1 0 1 0 1 95 0.99 1 0 0 1 0 1 1 0 96 0.995 1 0 0 1 0 1 1 1 97 1 1 0 0 1 1 0 0 0 98 1.005 1 0 0 1 1 0 0 1 99 1.01 1 0 0 1 1 0 1 0 9a 1.015 1 0 0 1 1 0 1 1 9b 1.02 1 0 0 1 1 1 0 0 9c 1.025 1 0 0 1 1 1 0 1 9d 1.03 1 0 0 1 1 1 1 0 9e 1.035 1 0 0 1 1 1 1 1 9f 1.04 1 0 1 0 0 0 0 0 a0 1.045 1 0 1 0 0 0 0 1 a1 1.05 1 0 1 0 0 0 1 0 a2 1.055 1 0 1 0 0 0 1 1 a3 1.06 1 0 1 0 0 1 0 0 a4 1.065 1 0 1 0 0 1 0 1 a5 1.07 1 0 1 0 0 1 1 0 a6 1.075 1 0 1 0 0 1 1 1 a7 1.08 1 0 1 0 1 0 0 0 a8 1.085 1 0 1 0 1 0 0 1 a9 1.09 1 0 1 0 1 0 1 0 aa 1.095 1 0 1 0 1 0 1 1 ab 1.1 1 0 1 0 1 1 0 0 ac 1.105 1 0 1 0 1 1 0 1 ad 1.11 1 0 1 0 1 1 1 0 ae 1.115 1 0 1 0 1 1 1 1 af 1.12 1 0 1 1 0 0 0 0 b0 1.125 1 0 1 1 0 0 0 1 b1 1.13 1 0 1 1 0 0 1 0 b2 1.135 1 0 1 1 0 0 1 1 b3 1.14 1 0 1 1 0 1 0 0 b4 1.145 1 0 1 1 0 1 0 1 b5 1.15 1 0 1 1 0 1 1 0 b6 1.155 1 0 1 1 0 1 1 1 b7 1.16 1 0 1 1 1 0 0 0 b8 1.165
12 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 0 1 1 1 0 0 1 b9 1.17 1 0 1 1 1 0 1 0 ba 1.175 1 0 1 1 1 0 1 1 bb 1.18 1 0 1 1 1 1 0 0 bc 1.185 1 0 1 1 1 1 0 1 bd 1.19 1 0 1 1 1 1 1 0 be 1.195 1 0 1 1 1 1 1 1 bf 1.2 1 1 0 0 0 0 0 0 c0 1.205 1 1 0 0 0 0 0 1 c1 1.21 1 1 0 0 0 0 1 0 c2 1.215 1 1 0 0 0 0 1 1 c3 1.22 1 1 0 0 0 1 0 0 c4 1.225 1 1 0 0 0 1 0 1 c5 1.23 1 1 0 0 0 1 1 0 c6 1.235 1 1 0 0 0 1 1 1 c7 1.24 1 1 0 0 1 0 0 0 c8 1.245 1 1 0 0 1 0 0 1 c9 1.25 1 1 0 0 1 0 1 0 ca 1.255 1 1 0 0 1 0 1 1 cb 1.26 1 1 0 0 1 1 0 0 cc 1.265 1 1 0 0 1 1 0 1 cd 1.27 1 1 0 0 1 1 1 0 ce 1.275 1 1 0 0 1 1 1 1 cf 1.28 1 1 0 1 0 0 0 0 d0 1.285 1 1 0 1 0 0 0 1 d1 1.29 1 1 0 1 0 0 1 0 d2 1.295 1 1 0 1 0 0 1 1 d3 1.3 1 1 0 1 0 1 0 0 d4 1.305 1 1 0 1 0 1 0 1 d5 1.31 1 1 0 1 0 1 1 0 d6 1.315 1 1 0 1 0 1 1 1 d7 1.32 1 1 0 1 1 0 0 0 d8 1.325 1 1 0 1 1 0 0 1 d9 1.33 1 1 0 1 1 0 1 0 da 1.335 1 1 0 1 1 0 1 1 db 1.34 1 1 0 1 1 1 0 0 dc 1.345 1 1 0 1 1 1 0 1 dd 1.35
13 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex voltage (v) 1 1 0 1 1 1 1 0 de 1.355 1 1 0 1 1 1 1 1 df 1.36 1 1 1 0 0 0 0 0 e0 1.365 1 1 1 0 0 0 0 1 e1 1.37 1 1 1 0 0 0 1 0 e2 1.375 1 1 1 0 0 0 1 1 e3 1.38 1 1 1 0 0 1 0 0 e4 1.385 1 1 1 0 0 1 0 1 e5 1.39 1 1 1 0 0 1 1 0 e6 1.395 1 1 1 0 0 1 1 1 e7 1.4 1 1 1 0 1 0 0 0 e8 1.405 1 1 1 0 1 0 0 1 e9 1.41 1 1 1 0 1 0 1 0 ea 1.415 1 1 1 0 1 0 1 1 eb 1.42 1 1 1 0 1 1 0 0 ec 1.425 1 1 1 0 1 1 0 1 ed 1.43 1 1 1 0 1 1 1 0 ee 1.435 1 1 1 0 1 1 1 1 ef 1.44 1 1 1 1 0 0 0 0 f0 1.445 1 1 1 1 0 0 0 1 f1 1.45 1 1 1 1 0 0 1 0 f2 1.455 1 1 1 1 0 0 1 1 f3 1.46 1 1 1 1 0 1 0 0 f4 1.465 1 1 1 1 0 1 0 1 f5 1.47 1 1 1 1 0 1 1 0 f6 1.475 1 1 1 1 0 1 1 1 f7 1.48 1 1 1 1 1 0 0 0 f8 1.485 1 1 1 1 1 0 0 1 f9 1.49 1 1 1 1 1 0 1 0 fa 1.495 1 1 1 1 1 0 1 1 fb 1.5 1 1 1 1 1 1 0 0 fc 1.505 1 1 1 1 1 1 0 1 fd 1.51 1 1 1 1 1 1 1 0 fe 1.515 1 1 1 1 1 1 1 1 ff 1.52
14 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 4) ? supply voltage, vcc -------------------------------------------------------------------------------- 4.5v to 5.5v ? junction temperature range ---------------------------- ------------------------------------------- ? 40 c to 125 c ? ambient temperature range ---------------------------- ------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) ? vcc to gnd ------------------------------------------------------------------------------------------- ? 0.3v to 6.5v ? pvcc to gnd ----------------------------------------------------------------------------------------- ? 0.3v to 15v ? rgnd to gnd ----------------------------------------------------------------------------------------- ? 0.3v to 0.3v ? tonset to gnd -------------------------------------------------------------------------------------- ? 0.3v to 28 ? bootx to phasex ---------------------------------------------------------------------------------- ? 0.3v to 15v ? phasex to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to 30v <20ns --------------------------------------------------------------------------------------------------- ? 10v to 35v ? lgatex to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to (vcc + 0.3v) <20ns --------------------------------------------------------------------------------------------------- ? 2v to (vcc + 0.3v) ? ugatex to gnd dc -------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) <20ns --------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) ? other pins ---------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) ? power dissipation, p d @ t a = 25 c wqfn-60l 7x7 --------------------------------------------------------------------------------------- 3.92w ? package thermal resistance (note 2) wqfn-60l 7x7, ja ---------------------------------------------------------------------------------- 25.5 c/w wqfn-60l 7x7, jc --------------------------------------------------------------------------------- 6.5 c/w ? junction temperature -------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c ? storage temperature range ---------------------------- ------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------- 200v
15 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v cc = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit supply input supply voltage v cc 4.5 5 5.5 v supply current i vcc v en = h, no switching -- 13 -- ma supply current at ps4 i vcc_ps4 v en = h, no switching -- 0.1 -- shutdown current i shdn v en = 0v -- -- 5 ? a reference and dac dac accuracy v fb vdac = 0.75v ?? 1.52v ? 0.5% 0 0.5% % of vid vdac = 0.5v ?? 0.745v ? 8 0 8 mv vdac = 0.25v ?? 0.495v ? 10 0 10 slew rate dynamic vid slew rate sr (s line) set vid fast -- 11.25 -- mv/ ? s set vid slow -- 5.625 -- dynamic vid slew rate sr (h, y, u line) set vid fast -- 33.75 -- mv/ ? s set vid slow -- 16.875 -- ea dc gain eagain r l = 47k ? 70 -- -- db gain-bandwidth product gbw c load = 5pf -- 5 -- mhz output voltage range v comp r l = 47k ? 0.5 -- 3.6 v max source/sink current i outea v comp = 2v -- 5 -- ma load line current gain amplifier input offset voltage v ilofs v imon = 1v ? 5 -- 5 mv current gain ailgain v imon ?? v vref = 1v v fb = v comp = 1v -- 1/3 -- a/a current sensing amplifier input offset voltage v oscs ? 0.5 -- 0.5 mv impedance at positive input risenxp 1 -- -- m ? current mirror gain amirror iimon/isenxn 0.97 1 1.03 a/a ton setting ton pin voltage v ton i rton = 26.8 ? a, vdac = 1v 0.9 1 1.1 v on-time setting t on i rton = 26.8 ? a, vdac = 1v 189 210 231 ns input current range i rton vdac = 1v 6 -- 70 ? a minimum off time t off vdac = 1v -- 180 -- ns ibias ibias pin voltage v ibias r ibias = 100k ? 1.9 2 2.1 v
16 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit protections under-voltage lockout threshold v uvlo falling edge 3.95 4.05 4.15 v ? v uvlo rising edge hysteresis -- 190 -- mv over-voltage protection threshold v ov respect to vid voltage vid + 300 vid + 350 vid + 400 mv lower limit to 1v 1300 1350 1400 mv negative voltage protection threshold v nv ? 100 ? 70 -- mv en and vr_reday en input voltage v ih respect to 1v, 70% 0.7 -- -- v v il respect to 1v, 30% -- -- 0.3 v leakage current of en ? 1 -- 1 ? a pgood pull low voltage v pgood i vr_ready = 10ma -- -- 0.13 v dvd (note 5) dvd input high voltage v ih v dvd = 2v or above, vr judge vin high 2 -- -- v dvd input low voltage v il v dvd = 1.3v or below, vr judge vin low -- -- 1.3 v serial vid and vr_hot vclk, vdio v ih respect to intel spec. with 50mv hysteresis 0.65 -- -- v v il -- -- 0.45 leakage current of vclk, vdio, alert and vr_hot i leak_in ? 1 -- 1 ? a vdio, alert and vr_hot pull low voltage i vdio = 10ma -- -- 0.13 v i alert = 10ma i vr_hot = 10ma vref vref voltage v ref 0.55 0.6 0.65 v adc digital imon setting v imon v imon ? v imon_ini = 1.6v -- 255 -- decimal v imon ? v imon_ini = 0.8v -- 128 -- decimal v imon ? v imon_ini = 0v -- 0 -- decimal psys digital psys setting v psys v psys = 3.2v -- 255 -- decimal v psys = 1.6v -- 128 -- decimal v psys = 0v -- 0 -- decimal
17 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit update period t imon -- 125 -- ? s tsen threshold for tmp_zone[7] transition v tsen 100 ? c -- 1.092 -- v tsen threshold for tmp_zone[6] transition 97 ? c -- 1.132 -- tsen threshold for tmp_zone[5] transition 94 ? c -- 1.176 -- tsen threshold for tmp_zone[4] transition 91 ? c -- 1.226 -- tsen threshold for tmp_zone[3] transition 88 ? c -- 1.283 -- tsen threshold for tmp_zone[2] transition 85 ? c -- 1.346 -- tsen threshold for tmp_zone[1] transition 82 ? c -- 1.418 -- tsen threshold for tmp_zone[0] transition 75 ? c -- 1.624 -- update period t tsen -- 100 -- ? s digital code of iccmax ciccmax1 v ref = 3.2v, v seti = 0.404v, v seta1 = 0.404v 61 64 67 decimal ciccmax2 v ref = 3.2v, v seti = 0.804v, v seta1 = 0.804v 125 128 131 decimal ciccmax3 v ref = 3.2v, v seti = 1.592v, v seta1 = 1.592v 251 254 255 decimal timing ugatex rising time t ugater 3nf load -- 25 -- ns ugatex falling time t ugatef 3nf load -- 12 -- ns lgatex rising time t lgater 3nf load -- 24 -- ns lgatex falling time t lgatef 3nf load -- 10 -- ns propagation delay t ugatepgh v bootx ?? v phasex = 12v see timing diagram -- 60 -- ns t ugatepdl -- 22 -- t lgatepdh see timing diagram -- 30 -- ns t lgatepdl -- 8 -- output ugatex drive source r ugatesr v boot ? v phase = 12v, i source = 100ma -- 1.7 -- ? ugatex drive sink r ugatesk v boot ? v phase = 12v, i sink = 100ma -- 1.4 -- ? lgatex drive source r lgatesr i source = 100ma -- 1.6 -- ? lgatex drive sink r lgatesk i sink = 100ma -- 1.1 -- ? pwm driving capability pwm source resistance r pw m_src -- 30 -- ? pwm sink resistance r pw m_snk -- 10 -- ?
18 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. (1) dvd input high voltage: dvd pin is an input pin of vr. vr always identify high level while the voltage given at dvd pin >= 2v. the high-low transition is within 1.3v ~2v. (2) dvd input low voltage: dvd pin is an input pin of vr. vr always identify low level while the voltage given at dvd pin <= 1.3v. the high-low transition is within 1.3v ~2v.
19 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit discrete mos RT3606BC 30 vcc 5v 44 dvd ibias 32 en 27 10 boot2 ugate2 phase2 lgate2 isen2n isen2p 9 isen1p isen1n 8 7 58 54 boot1 ugate1 phase1 lgate1 vcc pwm boot ugate phase lgate pgnd rt9624a isen3n i s e n 3 p p w m 3 1 5 6 en v i n vcc pwm boot ugate phase lgate 12v pgnd rt9624a pwma2 isena2p isena2n 37 38 47 en 12v v i n v i n v i n optional optional optional optional load v ss_sense v core_out v cc_sense isena1p isena1n 40 41 boota1 ugatea1 phasea1 lgatea1 v i n optional rgnda 33 fba 36 compa 35 vsena 34 optional optional optional v ssaxg_sense v ccaxg_sense rgnd 14 fb 11 comp 12 vsen 13 optional optional optional v ss_sense v cc_sense v cc_sense tsen 4 tsena 42 r ntc r ntc v in seta2 19 18 17 16 seta1 set3 set2 v ref 15 set1 pgood 2 23 vclk vdio 26 25 24 v ccio to cpu tonseta 43 3 tonset v in v in vref imon imona 20 22 21 r ntca v ref vr_hot alert gnd 61 (exposed pad) enable load v axg_out v ssaxg_sense v ccaxg_sense ofsm 28 ofsa/psys 29 ps4_dr 45 ps4_dr 60 59 57 56 55 53 48 49 50 51 pvcc 52 5v for v in = 19v 12v for v in =12v ps4_dr ps4_dr 0.47f/ x7r/0603 0.47f/ x7r/0603 0.47f/ x7r/0603 0.47f/ x7r/0603 0.47f/ x7r/0603 r1 510k r2 140k c1 0.1f r3 2.2 c2 2.2f r4 59k r5 69.8k r6 174k r7 64.9k r8 46.4k r9 12k r10 7.5k r11 3.32k r12 18.2k r13 11k r14 2.2 c3 0.22f r15 487k r16 2.2 c4 0.22f r17 412k r18 100k r87 1 c5 0.47f r19 13k r20 3.09k r ntc r22 16.5k 24.3k r23 r24 16k r25 15.8k r27 110 r26 nc r28 55 r29 75 r30 10k c6 470pf c7 56pf r31 12k r32 32.4k c9 c8 c11 c12 330pf c13 33pf r34 10k r35 34k c14 c15 c16 r36 93.1k r37 8.77k r38 93.1k r39 8.77k r40 2.2 c18 0.1f r41 0 r42 0 r43 1 c19 3.3nf l1 220nh/0.49m r44 1k c20 r45 r82 680 r46 2.2 c22 0.1f r47 0 r48 0 r49 1 c23 3.3nf r50 1k l2 220nh/0.49m c24 r51 r83 680 c25 1f r52 2.2 c26 0.1f r53 0 r54 0 r55 1 c27 3.3nf r56 1k l3 220nh/0.49m c28 r57 470f x 4 22f x 19 optional c48 c44 c45 r88 100 r89 100 r84 680 c37 1f r70 2.2 c38 0.1f r71 0 r73 1 c39 3.3nf r74 1k l6 220nh/0.49m c40 r75 r33 680 r72 0 r76 2.2 c40 0.1f r77 0 r78 0 r79 1 c43 3.3nf r81 1k l7 220nh/0.49m c10 r80 470f x 4 c46 c49 optional 22f x 14 c47 r90 100 r91 100 r21 680 r65 100k c50 22f r64 2.2 150k/4500 () ? 150k/4500 () ? 100k/4485 () ? 100k/4485 () ?
20 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics time (50 s/div) core vr ovp v core (500mv/div) ugate1 (20v/div) pgood (1v/div) lgate1 (10v/div) v in = 12v, vid = 0.9v time (100 s/div) core vr ocp v core (200mv/div) ugate1 (20v/div) pgood (1v/div) i load (60a/div) time (10 s/div) core vr dynamic vid down vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.9v to 0.6v, slew rate = slow, s-line v core (200mv/div) alert (1v/div) vdio v core vclk alert vdio time (10 s/div) core vr dynamic vid up vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.6v to 0.9v, slew rate = slow, s-line v core (200mv/div) alert (1v/div) v core vclk alert time (500 s/div) core vr power on from en v in = 12v, no load, vid = 0.8v, set2 pin tied to 5v v core (300mv/div) ugate1 (10v/div) pgood (1v/div) en (1v/div) time (50 s/div) core vr power off from en v in = 12v, no load, vid = 0.8v, set2 pin tied to 5v v core (300mv/div) ugate1 (10v/div) pgood (1v/div) en (1v/div)
21 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vimon vs. load current 0.0 0.5 1.0 1.5 2.0 2.5 020406080100 load current (a) vimon (v) time (50 s/div) core vr mode transient v in = 12v, vid = 0.9v, ps0 to ps2, i load = 1a v core vclk v core (20mv/div) ugate1 (20v/div) vlck (1v/div) lgate1 (5v/div) ugate1 lgate1 time (50 s/div) core vr mode transient v in = 12v, vid = 0.9v, ps2 to ps0, i load = 1a v core vclk v core (20mv/div) ugate1 (20v/div) vlck (1v/div) lgate1 (5v/div) ugate1 lgate1 time (5ms/div) core vr thermal monitioring v in = 12v, v tsen sweep from 1v to 2v v tsen (500mv/div) vr_hot (1v/div) time (10 s/div) core vr dynamic vid up vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.6v to 0.9v, slew rate = fast, s-line v core (200mv/div) alert (1v/div) vdio v core vclk alert time (500 s/div) axg vr power on from en v in = 12v, no load, vid = 0.8v, set2 pin tied to 5v v axg (300mv/div) ug_gt1 (10v/div) pgood (1v/div) en (1v/div)
22 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (500 s/div) axg vr power off from en v in = 12v, no load, vid = 0.8v, set2 pin tied to 5v v axg (300mv/div) ug_gt1 (10v/div) pgood (1v/div) en (1v/div) time (50 s/div) axg vr ovp v axg (500mv/div) ug_gt1 (20v/div) pgood (1v/div) lg_gt1 (5v/div) v in = 12v, vid = 0.9v pgood v axg time (10 s/div) axg vr dynamic vid up vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.6v to 0.9v, slew rate = fast, s-line v axg (200mv/div) alert (1v/div) vdio v axg vclk alert time (10 s/div) axg vr dynamic vid up vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.6v to 0.9v, slew rate = slow, s-line v axg (200mv/div) alert (1v/div) vdio v axg vclk alert time (100 s/div) axg vr ocp v axg (200mv/div) ug_gt1 (20v/div) pgood (1v/div) i load (50a/div) pgood v axg time (10 s/div) axg vr dynamic vid down vdio (1v/div) vclk (1v/div) v in = 12v, vid = 0.9v to 0.6v, slew rate = slow, s-line v axg (200mv/div) alert (1v/div) vdio vclk alert v axg
23 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vimona vs. load current 0.0 0.5 1.0 1.5 2.0 2.5 0 20406080100 load current (a) vimona (v) time (5ms/div) axg vr thermal monitioring v in = 12v, v tsena sweep from 1v to 2v v tsena (500mv/div) vr_hot (1v/div) time (50 s/div) axg vr mode transient v in = 12v, vid = 0.9v, ps0 to ps2, i load = 1a v axg vclk v axg (20mv/div) ug_gt1 (20v/div) vlck (1v/div) lg_gt1 (5v/div) ugate1 lgate1 time (50 s/div) axg vr mode transient v in = 12v, vid = 0.9v, ps2 to ps0, i load = 1a vclk v axg (20mv/div) ug_gt1 (20v/div) vlck (1v/div) lg_gt1 (5v/div) ugate1 lgate1 v axg
24 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications information the RT3606BC includes two voltage rails : a 3/2/1 multiphase synchronous buck controller, the core vr, and a 2/1 multiphase synchronous buck controller, the axg vr, designed to meet intel imvp8 compatible cpus specification with a serial svid control interface. the controller uses an adc to implement the all kinds of settings to save total pin number for easy use and increasing pcb space utilization. RT3606BC is used in notebook, desktop computers and servers. general loop function g-navp tm control mode the RT3606BC adopts the g-navp tm controller, which is a current mode constant on-time control with dc offset cancellation. the approach can not only improve dc offset problem for increasing system accuracy but also provide fast transient response. when current feedback signal reaches comp signal, the RT3606BC generates an on- time width to achieve pwm modulation. figure 1 shows the basic g-navp tm behavior waveforms in continuous conduct mode (ccm). pwm1 pwm2 pwm3 pwm4 current feedback signal comp signal figure 1 (a). g-navp tm ccm behavior waveforms in ccm in steady state pwm1 pwm2 pwm3 pwm4 current fee dback signal comp signal figure 1 (b). g-navp tm ccm behavior waveforms in ccm in load transient. diode emulation mode (dem) as well-known, the dominate power loss is switching related loss during light load, hence vr needs to be operated in asynchronous mode (or called discontinuous conduct mode, dcm) to reduce switching related loss since switching frequency is dependent on loading in the asynchronous mode. the RT3606BC can operate in diode emulation mode (dem) to improve light load efficiency. in dem operation, the behavior of the low side mosfet(s) needs to work like a diode, that is, the low side mosfet(s) will be turned on when the phase voltage is a negative value, i.e. the inductor current follows from source to drain of low-side mosfet(s). and the low-side mosfet(s) will be turned off when phase voltage is a positive value, i.e. reversed current is not allowed. figure 2 shows the control behavior in dem. figure 3 shows the g-navp tm operation in dem to illustrate the control behaviors. when load decreases, the discharge time of output capacitors increases during ugate and lgate are turned off. hence, the switching frequency and switching loss will be reduced to improve efficiency in light load condition.
25 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. inductor current phase node ugate lgate figure 2. diode emulation mode (dem) in steady state figure 3. g-navp tm operation in dem. (a) : the load is lighter, output capacitor discharge slope is smaller and the switching frequency is lower. (b) : the load is increasing, output capacitor discharge slope is increased and switching frequency is increased, too. output capacitor discharge slope ugate lgate comp signal inductor current signal output capacitor discharge slope ugate lgate comp signal inductor current signal figure 3. (a) figure 3. (b)
26 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. phase interleaving function RT3606BC is a multiphase controller, which has a phase interleaving function, 120 degree phase shift for 3-phase operation and 180 degree phase shift for 2-phase operation which can help reduce output voltage ripple and emi problem. multi-function pin setting mechanism for reducing total pin number of package, set [1:3] and seta[1:2] pins adopt the multi-function pin setting mechanism in the RT3606BC. set [1:3] and seta[1:2] are used to set core vr and axg vr, respectively. figure 4 illustrates this operating mechanism. the voltage at vref pin will be pulled up to 3.2v after power ready (por). first, external voltage divider is used to set the function1 and then internal current source 80 a is used to set the function2. the setting voltage of function1 and function2 can be represented as function1 function2 r2 v3.2v r1 r2 r1 r2 v80 r1 r2 ? ?? ? ? ??? ? all function setting will be done within 500 s after power ready (por), and the voltage at vref pin will fix to 0.6v after all function setting over. if v function1 and v function2 are determined, r1 and r2 can be calculated as follows : in addition, richtek provides a microsoft excel-based spreadsheet to help design the setx and setax resistor network for RT3606BC. figure 4. multi-function pin setting mechanism v ref r1 r2 set x 80a function 1 register function 2 register adc function 1 <5:0> function 2 <5:0> (seta x ) v ref r1 r2 set x 80a function 1 register function 2 register adc function 1 <5:0> function 2 <5:0> (seta x ) connects a r3 resistor from setx pin or setax pin to the middle node of voltage divider can help to fine tune the set voltage of function2, which does not affect the set voltage of function1. the figure 5 shows the setting method and the set voltage of function 1 and function2 can be represented as : function1 function2 r2 v3.2v r1 r2 r1 r2 v80 r3 r1 r2 ? ?? ? ? ?? ??? ?? ? ?? function2 function1 3.2v v r1 80 v ? ? ? ?? function1 function1 r1 v r2 3.2v v ? ? ? by the way, set1 and set2 are used to set core rail setting and seta1 and seta2 are used to set axg rail setting. the setting of set3 is suitable for both core rail and axg rail. table 2 summarizes the overall pin setting function. table 3 and table 4 show the set3 pin setting function table.
27 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. pin setting function table function1 function2 set1 (core rail) iccmax dvid threshold over current protection (ocp) threshold set2 (core rail) dvid width ramp amplitude quick response (qr) threshold quick response (qr) width set3 (core / axg rail) vr address enable zero load-line enable anti-overshoot function anti-overshoot behavior current gain ai enable psys function enable high switching frequency ramp dvid slew rate disable dvid compensation decrease gtu/sa ramp amplitude (only active in max phase = 1 application) seta1 (axg rail) iccmaxa dvid threshold over current protection (ocp) threshold seta2 (axg rail) dvid width ramp amplitude quick response (qr) threshold quick response (qr) width ? table 3. set3 pin setting for vr address, enable zero load-line, enable anti-overshoot function, anti-overshoot behavior, and current gain ai set3 r2 v = x 3.2v r1+r2 vr address zero load line anti_ovs ahti_ovs behavior ai gain min typical max unit 0.000 10.948 21.896 mv core : 00 axg : 01 core : with ll axg : with ll disable high-low-floating 1x 25.024 35.973 46.921 mv 2x 50.049 60.997 71.945 mv high-floating 1x 75.073 86.022 96.970 mv 2x 100.098 111.046 121.994 mv enable high-low-floating 1x 125.122 136.070 147.019 mv 2x 150.147 161.095 172.043 mv high-floating 1x 175.171 186.119 197.067 mv 2x 200.196 211.144 222.092 mv core : with ll axg : w/o ll disable high-low-floating 1x 225.220 236.168 247.116 mv 2x 250.244 261.193 272.141 mv high-floating 1x 275.269 286.217 297.165 mv 2x 300.293 311.241 322.190 mv enable high-low-floating 1x 325.318 336.266 347.214 mv 2x 350.342 361.290 372.239 mv high-floating 1x 375.367 386.315 397.263 mv 2x ?
28 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set3 r2 v = x 3.2v r1+r2 vr address zero load line anti_ovs ahti_ovs behavior ai gain min typical max unit 400.391 411.339 422.287 mv core : 00 axg : 02 core : with ll axg : with ll disable high-low-floating 1x 425.415 436.364 447.312 mv 2x 450.440 461.388 472.336 mv high-floating 1x 475.464 486.413 497.361 mv 2x 500.489 511.437 522.385 mv enable high-low-floating 1x 525.513 536.461 547.410 mv 2x 550.538 561.486 572.434 mv high-floating 1x 575.562 586.510 597.458 mv 2x 600.587 611.535 622.483 mv core : with ll axg : w/o ll disable high-low-floating 1x 625.611 636.559 647.507 mv 2x 650.635 661.584 672.532 mv high-floating 1x 675.660 686.608 697.556 mv 2x 700.684 711.632 722.581 mv enable high-low-floating 1x 725.709 736.657 747.605 mv 2x 750.733 761.681 772.630 mv high-floating 1x 775.758 786.706 797.654 mv 2x 800.782 811.730 822.678 mv core : 01 axg : 00 core : with ll axg : with ll disable high-low-floating 1x 825.806 836.755 847.703 mv 2x 850.831 861.779 872.727 mv high-floating 1x 875.855 886.804 897.752 mv 2x 900.880 911.828 922.776 mv enable high-low-floating 1x 925.904 936.852 947.801 mv 2x 950.929 961.877 972.825 mv high-floating 1x 975.953 986.901 997.849 mv 2x 1000.978 1011.926 1022.874 mv core : w/o ll axg : with ll disable high-low-floating 1x 1026.002 1036.950 1047.898 mv 2x 1051.026 1061.975 1072.923 mv high-floating 1x 1076.051 1086.999 1097.947 mv 2x 1101.075 1112.023 1122.972 mv enable high-low-floating 1x 1126.100 1137.048 1147.996 mv 2x 1151.124 1162.072 1173.021 mv high-floating 1x 1176.149 1187.097 1198.045 mv 2x ?
29 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set3 r2 v = x 3.2v r1+r2 vr address zero load line anti_ovs ahti_ovs behavior ai gain min typical max unit 1201.173 1212.121 1223.069 mv core : 01 axg : 03 core : with ll axg : with ll disable high-low-floating 1x 1226.197 1237.146 1248.094 mv 2x 1251.222 1262.170 1273.118 mv high-floating 1x 1276.246 1287.195 1298.143 mv 2x 1301.271 1312.219 1323.167 mv enable high-low-floating 1x 1326.295 1337.243 1348.192 mv 2x 1351.320 1362.268 1373.216 mv high-floating 1x 1376.344 1387.292 1398.240 mv 2x 1401.369 1412.317 1423.265 mv core : with ll axg : w/o ll disable high-low-floating 1x 1426.393 1437.341 1448.289 mv 2x 1451.417 1462.366 1473.314 mv high-floating 1x 1476.442 1487.390 1498.338 mv 2x 1501.466 1512.414 1523.363 mv enable high-low-floating 1x 1526.491 1537.439 1548.387 mv 2x 1551.515 1562.463 1573.412 mv high-floating 1x 1576.540 1587.488 1598.436 mv 2x ? ?
30 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 4. set3 pin setting for enable psys function, enable high switching frequency ramp, dvid slew rate, disable dvid compensation, decrease gtu/sa ramp amplitude (only active in max phase =1 application) set3 r1 r2 v80 a r1 r2 ? ??? ? en psys en high freq ramp dvid sr disable divd compensation decrease gtu/sa ramp (only active as max phase number =1) min typical max unit 0.000 10.948 21.896 mv disable disable 33.75mv/ ? s disable disable 25.024 35.973 46.921 mv 50.049 60.997 71.945 mv enable 75.073 86.022 96.970 mv 100.098 111.046 121.994 mv enable disable 125.122 136.070 147.019 mv 150.147 161.095 172.043 mv enable 175.171 186.119 197.067 mv 200.196 211.144 222.092 mv 11.25m v/ ? s disable disable 225.220 236.168 247.116 mv 250.244 261.193 272.141 mv enable 275.269 286.217 297.165 mv 300.293 311.241 322.190 mv enable disable 325.318 336.266 347.214 mv 350.342 361.290 372.239 mv enable 375.367 386.315 397.263 mv 400.391 411.339 422.287 mv enable 33.75mv/ ? s disable disable 425.415 436.364 447.312 mv 450.440 461.388 472.336 mv enable 475.464 486.413 497.361 mv 500.489 511.437 522.385 mv enable disable 525.513 536.461 547.410 mv 550.538 561.486 572.434 mv enable 575.562 586.510 597.458 mv 600.587 611.535 622.483 mv 11.25m v/ ? s disable disable 625.611 636.559 647.507 mv 650.635 661.584 672.532 mv enable 675.660 686.608 697.556 mv 700.684 711.632 722.581 mv enable disable 725.709 736.657 747.605 mv 750.733 761.681 772.630 mv enable 775.758 786.706 797.654 mv
31 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set3 r1 r2 v80 a r1 r2 ? ??? ? en psys en high freq ramp dvid sr disable divd compensation decrease gtu/sa ramp (only active as max phase number = 1) min typical max unit 800.782 811.730 822.678 mv enable disable 33.75mv/ ? s disable disable 825.806 836.755 847.703 mv 850.831 861.779 872.727 mv enable 875.855 886.804 897.752 mv 900.880 911.828 922.776 mv enable disable 925.904 936.852 947.801 mv 950.929 961.877 972.825 mv enable 975.953 986.901 997.849 mv 1000.978 1011.926 1022.874 mv 11.25m v/ ? s disable disable 1026.002 1036.950 1047.898 mv 1051.026 1061.975 1072.923 mv enable 1076.051 1086.999 1097.947 mv 1101.075 1112.023 1122.972 mv enable disable 1126.100 1137.048 1147.996 mv 1151.124 1162.072 1173.021 mv enable 1176.149 1187.097 1198.045 mv 1201.173 1212.121 1223.069 mv enable 33.75mv/ ? s disable disable 1226.197 1237.146 1248.094 mv 1251.222 1262.170 1273.118 mv enable 1276.246 1287.195 1298.143 mv 1301.271 1312.219 1323.167 mv enable disable 1326.295 1337.243 1348.192 mv 1351.320 1362.268 1373.216 mv enable 1376.344 1387.292 1398.240 mv 1401.369 1412.317 1423.265 mv 11.25m v/ ? s disable disable 1426.393 1437.341 1448.289 mv 1451.417 1462.366 1473.314 mv enable 1476.442 1487.390 1498.338 mv 1501.466 1512.414 1523.363 mv enable disable 1526.491 1537.439 1548.387 mv 1551.515 1562.463 1573.412 mv enable 1576.540 1587.488 1598.436 mv ?
32 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v ref r1 r2 80a function 1 register function 2 register adc function 1 <5:0> function 2 <5:0> r3 set x (seta x ) v ref r1 r2 80a function 1 register function 2 register adc function 1 <5:0> function 2 <5:0> r3 set x (seta x ) figure 5. multi-function pin setting mechanism with a r3 resistor to fine tune the set voltage of function2 vr rail addressing setting the vr address of RT3606BC can be flipped by setting the voltage on set3 with an external voltage divider as shown in figure 6. the voltage at vref pin will be pulled up to 3.2v after power ready (por) and the voltage at vref pin will fix to 0.6v within 500 s after power ready (por). besides, when axg rail address is set to 2, the boot voltage of axg rail is 1.05v. figure 6. vr rail addressing and zero load-line setting for set3 v ref r1 r2 function 1 register adc function 1 <5:0> set3 anti-overshoot and anti-overshoot behavior the anti-overshoot function can be enabled or disabled by setting the voltage on set3 with an external voltage divider. during the anti-overshoot function is triggered, the high side and low side mos will both turn off. therefore, the output voltage adds the forward voltage of the mos parasitic body diode will crosses on the inductor to speed up the discharge speed and eases the overshoot magnitude. however, if the mos driver has tri-state delay time, the performance of the anti-overshoot function will be degenerated. to prevent this phenomenon, RT3606BC provides two kinds of anti-overshoot low side mos behavior. with the driver has tri-state delay time, the behavior of anti-overshoot can choose as high-low-floating, and with the driver without tri-state delay time, the behavior of anti- overshoot can choose as high-floating. high switching frequency ramp the switching frequency of RT3606BC can support from 300khz to 1.1mhz, however, with higher switching frequency, the ramp is needed to increase simultaneously to improve the system stability and smooth the mode transient performance. as switching is higher than 550khz, the high switching frequency ramp is suggested to be enabled. the high switching frequency ramp can be enabled or disabled by the internal current source 80 a and the parallel of the high low side resistor on set3 pin. decrease gtu/sa ramp amplitude (only active in max phase = 1 application) if RT3606BC apply in gtu or sa application and the maximum phase number is 1. the ramp amplitude will automatically increase to improve the stability. this function can be disabled to improve the transient performance by the internal current source 80 a and the parallel of the high low side resistor on set3 pin.
33 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. tsen(a) r1 r2 r ntc - + 1.092v vddio vr_hot 80a figure 8. vr_hot circuit power ready (por) detection during start-up, the RT3606BC detects the voltage at the voltage input pins: v cc , en and dvd. when v cc > 4.34v and v dvd > 2v, the RT3606BC recognizes the power state of system to be ready (por = high) and waits for enable command at the en pin. after por = high and v en > 0.7v, the RT3606BC will enter start-up sequence. if the voltage at any voltage pin drops below low threshold (por = low), the RT3606BC will enter power down sequence and all the functions will be disabled. normally, connecting system voltage v tt (1.05v) to the en pin and power stage vin (12v, through a voltage divider) to the dvd pin is recommended. 2ms (max) after the chip has been enabled, the svid circuitry will be ready. all the protection latches (ovp, ocp, uvp) will be cleared only by vcc. the condition of ven = low will not clear these latches. figure 9 and figure 10 show the por detection and the timing chart for por process, respectively. under voltage lockout (uvlo) during normal operation, if the voltage at the vcc drops below por threshold 3.95v (min) or dvd voltage drops below por threshold 1.3v, the vr triggers uvlo. the uvlo protection forces all high-side mosfets and low- side mosfets off by shutting down internal pwm logic drivers. tsen, tsena and vr_hot the vr_hot signal is an open-drain signal which is used for vr thermal protection. when the sensed voltage in tsen(a) pin is less than 1.092, the vr_hot signal will be pulled-low to notify cpu that the thermal protection needs to work. according to intel vr definition, vr_hot signal needs acting if vr power chain temperature exceeds 100 c. placing an ntc thermistor at the hottest area in the vr power chain and its connection is shown in figure 8, to design the voltage divider elements (r1, r2 and ntc) so that vtsen(a) = 1.092v at 100 c. the resistance error of tsen network is recommended to be 1% or smaller. tsen( ) ntc (100 c v80 (r1//(r2 r )) ? ? ?? ? precise reference current generation, ibias analog circuits need very precise reference voltage/current to drive/set these analog devices. the RT3606BC provides a 2v voltage source at the ibias pin, and a 100k resistor is required to be connected between the ibias pin and analog ground to generate a very precise reference current. through this connection, the RT3606BC will generate a 20 a current from the ibias pin to analog ground, and this 20 a current will be mirrored inside the RT3606BC for internal use. the ibias pin can only be connected with a 100k resistor to gnd for internal analog circuit use. the resistance error of this resistor is recommended to be 1% or smaller. figure 7 shows the ibias setting circuit. + - ibias 100k current mirror 2v 20a figure 7. ibias setting circuit
34 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 9. por detection figure 10. timing chart for por process vcc dvd por en svid invalid invalid valid 2ms core vr phase disable (before por) the number of active phases is determined by the internal circuitry that monitors the isenxn voltages during startup. normally, the vr operates as a 3-phase pwm controller. pulling isen3n to vcc programs a 2-phase operation, and pulling isen2n and isen3n to vcc programs a 1- phase operation. before por, vr detects whether the voltages of isen2n and isen3n are higher than ? vcc ? 1v ? respectively to decide how many phases should be active. phase selection is only active during por. when por = high, the number of active phases is determined and latched. the unused isenxp pins are recommended to be connected to vcc and unused pwm pins can be left floating. no load offset (platform) the core vr features no load offset function which provides the possibility of wide range positive offset of output voltage. users can disable offset function by simply connecting o fsm pin to gnd. figure 11 shows a voltage divider used to set no load offset voltage. no load offset voltage setting is : () ofs_core ofsm v 0.4 v 1.7 ?? ? dac + + + svid offset register svid vid register pin offset register adc v cc r1 r2 ofsm vid_ref figure 11. no loa d offset circuit switching frequency setting r t3606bc is one kind of constant on-time control. the patented ccrcot (constant current ripple cot) technology can generate an adaptive on-time, the on-time will vary with the input voltage and vid code to obtain a constant current ripple, so that the output voltage ripple can be controlled nearly like a constant as different input and output voltages change. for core vr, connect a resistor r ton between input terminal and tonset pin to set the on-time width. ton on dac in dac ton dac on dac in dac r4.73p1.2 t(v1.2) vv r4.73pv t(v1.2) vv ?? ?? ? ?? ?? ? ?? sw(max) on_ls,max ll ls on_ls,max on_hs,max on_ls,max in(max) on d on,var d ls hs ls f r icctdc vid1 dcr n r nn rr r icctdc icctdc vtttt nn n nn ? ?? ??? ?? ?? ?? ?? ?? ?? ?? ? ??? ?? ? ?? ?? ?? ?? ?? ?? ?? where f sw(max) is the maximum switching frequency, vid1 is the typical vid of application, v in(max) is the maximum application input voltage, icctdc is the thermal design current of application, n is the phase number. the r on_hs,max is the maximum equivalent high-side r ds(on) , the range of v ofs_core is between ? 500mv and 590mv and the resolution is 10mv. for example, a 100mv no load offset requirement, v ofsm needs to be set as 1.95v. for better efficiency of the given load range, the maximum switching frequency is suggested to be : + - + - + - por chip enable 4.34v 2v 0.7v cp cp cp vcc dvd en r1 r2 v tt 1.05v v in 5v
35 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. lx csx i dcr isenxn r ? ? where lx/dcr = r x c x is held. the method can get high efficiency performance, but dcr value will be drifted by temperature, a ntc resistor should add in the resistor network in the imon pin to achieve dcr thermal compensation. in rt3606b c design, the resistance of r csx is restricted to 680 ; moreover, the error of r csx is recommended to be 1% or smaller. isenxp isenxn l x dcr r x c x v core + - r csx i lx i senxn figure 12. lossless current sense method total current sense total current sense method is a patented topology, unlike conventional current sense method need a ntc resistor in per phase current loop for thermal compensation. RT3606BC adopts the total current sense method requiring o nly one ntc resistor for thermal compensation, and ntc resistor cost can be saved by using this method. figure 13 shows the total current sense method which connects the resistor network between imon pin and vref pin to set a part of current loop gain for load line (droop) setting and set accurate over current protection. ??? imon ref eq l1 l2 l3 cs dcr v v = r (i +i +i ) r r eq includes a ntc resistor to compensate dcr thermal drifting for high accuracy load-line (droop). v core isen1p isen1n l dcr r c + - r cs i l1 i sen1n isen2p isen2n l dcr r c + - r cs i l2 i sen2n isen3p isen3n l dcr r c + - r cs i l3 i sen3n v ref imon r ntc r eq figure 13. total current sense method and n hs is the number of high-side mosfets; r on_ls,max is the maximum equivalent low-side r ds(on) , and n ls is the number of low-side mosfets. t d is the summation of the high-side mosfet delay time and the rising time, t on,var is the t on variation value. dcr is the inductor dcr, and r ll is the loadline setting. in addition, richtek provides a microsoft excel-based spreadsheet to help design the r ton for RT3606BC. when load increases, on-time keeps constant. the off- time width will be reduced so that loading can load more power from input terminal to regulate output voltage. hence the loading current usually increases in case the switching frequency also increases. higher switching frequency operation can reduce power components' size and pcb space, trading off the whole efficiency since switching related switching related loss increases, vice versa. per phase current sense in the RT3606BC, the current signal is used for load-line setting and over-current protection (ocp). the inductor current sense method adopts the lossless current sensing for allowing high efficiency as illustrated in figure 12. when inductance and dcr time constant is equal to r x c x filter network time constant, a voltage i lx x dcr will drop on c x to generate inductor current signal. according to the figure 12, the isenxn is as follows : load-line setting (droop) the g-navp tm topology can set load-line (droop) via the current loop and the voltage loop, the load-line is a slope between load current i cc and output voltage v core as shown figure 14. figure 15 shows the voltage control and current loop. by using the both loops, the load-line (droop) can be set easily. the load-line set equation is : ?? eq cs i ll v 1dcr r 3r a rm ar2 r1 ?? ?? ?
36 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. i cc v coee load line slope = -r ll r ll x i cc figure 14. load-line (droop) + - r2 r1 vid c r l dcr i l1.2.3 + - isen[1:3]n isen[1:3]p r cs i sen1n + i sen2n + i sen3n + - 1/3 + - voltage loop ton generator r eq imon r ntc v ref v core figure 15. voltage loop and current loop compensator design the compensator of RT3606BC doesn?t need a complex type ii or type iii compensator to optimize control loop performance. it can adopt a simple type i compensator (one pole, one zero) in g-navp tm topology to achieve constan t output impedance design for intel imvp8 acll specification. the one pole one zero compensator is shown as figure 16, the transfer function of compensator should be design as following transfer function to achieve constant output impedance, i.e. zo(s) = load-line slope in the entire frequency range 1 1 i con ll esr s a fsw g(s) rs ? ? ? ? ? ? where a i is current loop gain, r ll is load line, f sw is switching frequency and esr is a pole that should be located at 1 / (c out x esr). then the c1 and c2 should be designed as sw 1 c1 r1 f ? ?? out c esr c2 r2 ? ? + - r2 r1 vid c2 c1 figure 16. type i compensator differential remote sense setting the vr provides differential remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu contains on-die sense pins, v cc_sense and v ss_sense . connect rg nd to v ss_sense and connect fb to v cc_sense with a resistor to build the negative input path of the error amplifier as shown in figure 17. the v dac and the precision voltage reference are referred to rgnd for accurate remote sensing. cpu v cc_sense - + fb rgnd ea - + vid r1 cpu v ss_sense r2 v out c out figure 17. remote sensing circuit maximum processor current setting, iccmax the maximum processor current iccmax can be set by the set1 pin. iccmax register is set by an external voltage divider with the multi-function mechanism. the table 5 sho ws the iccmax setting on the set1 pin. for example, iccmax = 80a, the v iccmax needs to set as 0.503 typical. additionally, v imon ? v ref needs to be set as 1.6v at iccmax when the maximum phase > 1. as in 1-phase application, the v imon ? v ref needs to be set as 0.4v at iccmax. the iccmax alert signal will be pulled to low level if v imon ? v ref = 1.6v (for maximum phase > 1) or v imon ? v ref = 0.4 (for 1-phase application).
37 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 5. set1 pin setting in iccmax set1 r2 v3.2v r1 r2 ?? ? iccmax unit min typical max unit 0.000 3.128 6.256 mv 0 a 12.512 15.640 18.768 mv 2 a 25.024 28.152 31.281 mv 4 a 37.537 40.665 43.793 mv 6 a 50.049 53.177 56.305 mv 8 a 62.561 65.689 68.817 mv 10 a 75.073 78.201 81.329 mv 12 a 87.586 90.714 93.842 mv 14 a 100.098 103.226 106.354 mv 16 a 112.610 115.738 118.866 mv 18 a 125.122 128.250 131.378 mv 20 a 137.634 140.762 143.891 mv 22 a 150.147 153.275 156.403 mv 24 a 162.659 165.787 168.915 mv 26 a 175.171 178.299 181.427 mv 28 a 187.683 190.811 193.939 mv 30 a 200.196 203.324 206.452 mv 32 a 212.708 215.836 218.964 mv 34 a 225.220 228.348 231.476 mv 36 a 237.732 240.860 243.988 mv 38 a 250.244 253.372 256.500 mv 40 a 262.757 265.885 269.013 mv 42 a 275.269 278.397 281.525 mv 44 a 287.781 290.909 294.037 mv 46 a 300.293 303.421 306.549 mv 48 a 312.805 315.934 319.062 mv 50 a 325.318 328.446 331.574 mv 52 a 337.830 340.958 344.086 mv 54 a 350.342 353.470 356.598 mv 56 a 362.854 365.982 369.110 mv 58 a 375.367 378.495 381.623 mv 60 a 387.879 391.007 394.135 mv 62 a 400.391 403.519 406.647 mv 64 a 412.903 416.031 419.159 mv 66 a 425.415 428.543 431.672 mv 68 a 437.928 441.056 444.184 mv 70 a 450.440 453.568 456.696 mv 72 a 462.952 466.080 469.208 mv 74 a set1 r2 v3.2v r1 r2 ?? ? iccmax unit min typical max unit 475.464 478.592 481.720 mv 76 a 487.977 491.105 494.233 mv 78 a 500.489 503.617 506.745 mv 80 a 513.001 516.129 519.257 mv 82 a 525.513 528.641 531.769 mv 84 a 538.025 541.153 544.282 mv 86 a 550.538 553.666 556.794 mv 88 a 563.050 566.178 569.306 mv 90 a 575.562 578.690 581.818 mv 92 a 588.074 591.202 594.330 mv 94 a 600.587 603.715 606.843 mv 96 a 613.099 616.227 619.355 mv 98 a 625.611 628.739 631.867 mv 100 a 638.123 641.251 644.379 mv 102 a 650.635 653.763 656.891 mv 104 a 663.148 666.276 669.404 mv 106 a 675.660 678.788 681.916 mv 108 a 688.172 691.300 694.428 mv 110 a 700.684 703.812 706.940 mv 112 a 713.196 716.325 719.453 mv 114 a 725.709 728.837 731.965 mv 116 a 738.221 741.349 744.477 mv 118 a 750.733 753.861 756.989 mv 120 a 763.245 766.373 769.501 mv 122 a 775.758 778.886 782.014 mv 124 a 788.270 791.398 794.526 mv 126 a 800.782 803.910 807.038 mv 128 a 813.294 816.422 819.550 mv 130 a 825.806 828.935 832.063 mv 132 a 838.319 841.447 844.575 mv 134 a 850.831 853.959 857.087 mv 136 a 863.343 866.471 869.599 mv 138 a 875.855 878.983 882.111 mv 140 a 888.368 891.496 894.624 mv 142 a 900.880 904.008 907.136 mv 144 a 913.392 916.520 919.648 mv 146 a 925.904 929.032 932.160 mv 148 a 938.416 941.544 944.673 mv 150 a
38 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set1 r2 v3.2v r1 r2 ?? ? iccmax unit min typical max unit 950.929 954.057 957.185 mv 152 a 963.441 966.569 969.697 mv 154 a 975.953 979.081 982.209 mv 156 a 988.465 991.593 994.721 mv 158 a 1000.978 1004.106 1007.234 mv 160 a 1013.490 1016.618 1019.746 mv 162 a 1026.002 1029.130 1032.258 mv 164 a 1038.514 1041.642 1044.770 mv 166 a 1051.026 1054.154 1057.283 mv 168 a 1063.539 1066.667 1069.795 mv 170 a 1076.051 1079.179 1082.307 mv 172 a 1088.563 1091.691 1094.819 mv 174 a 1101.075 1104.203 1107.331 mv 176 a 1113.587 1116.716 1119.844 mv 178 a 1126.100 1129.228 1132.356 mv 180 a 1138.612 1141.740 1144.868 mv 182 a 1151.124 1154.252 1157.380 mv 184 a 1163.636 1166.764 1169.892 mv 186 a 1176.149 1179.277 1182.405 mv 188 a 1188.661 1191.789 1194.917 mv 190 a 1201.173 1204.301 1207.429 mv 192 a 1213.685 1216.813 1219.941 mv 194 a 1226.197 1229.326 1232.454 mv 196 a 1238.710 1241.838 1244.966 mv 198 a 1251.222 1254.350 1257.478 mv 200 a 1263.734 1266.862 1269.990 mv 202 a 1276.246 1279.374 1282.502 mv 204 a 1288.759 1291.887 1295.015 mv 206 a 1301.271 1304.399 1307.527 mv 208 a 1313.783 1316.911 1320.039 mv 210 a 1326.295 1329.423 1332.551 mv 212 a 1338.807 1341.935 1345.064 mv 214 a 1351.320 1354.448 1357.576 mv 216 a 1363.832 1366.960 1370.088 mv 218 a 1376.344 1379.472 1382.600 mv 220 a 1388.856 1391.984 1395.112 mv 222 a 1401.369 1404.497 1407.625 mv 224 a 1413.881 1417.009 1420.137 mv 226 a set1 r2 v3.2v r1 r2 ?? ? iccmax unit min typical max unit 1426.393 1429.521 1432.649 mv 228 a 1438.905 1442.033 1445.161 mv 230 a 1451.417 1454.545 1457.674 mv 232 a 1463.930 1467.058 1470.186 mv 234 a 1476.442 1479.570 1482.698 mv 236 a 1488.954 1492.082 1495.210 mv 238 a 1501.466 1504.594 1507.722 mv 240 a 1513.978 1517.107 1520.235 mv 242 a 1526.491 1529.619 1532.747 mv 244 a 1539.003 1542.131 1545.259 mv 246 a 1551.515 1554.643 1557.771 mv 248 a 1564.027 1567.155 1570.283 mv 250 a 1576.540 1579.668 1582.796 mv 252 a 1589.052 1592.180 1595.308 mv 254 a
39 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dynamic vid (dvid) compensation when vid transiti on event occurs, a charger current will be generated in the loop to cause dvid performance. however, the dvid performance will be deteriorated by this induced charger current, this phenomenon is called droop effect. the droop effect is shown in figure 18, when vid up transition occurs, the output capacitor will be charged by inductor current. since current signal is sensed in inductor, an induced charge current will appear in control loop. the induced charge current will produce a voltage drop in r1 to cause output voltage to have a droop effect. due to this, vid transition performance will be deteriorated. v in gate driver q1 q2 l r esr c o2 cpu c2 charge current induced charge current signal c o1 ai r1 r2 c1 + - ea + - comp ccrcot t on vid transition i droop vid output voltage vin vid figure 18. droop eff ect in vid transition RT3606BC provide a dvid compensation function. a virtual charge current signal can be established by the set1/set2 pins to cancel the real induced charge current signal and the virtual charge current signal is defined in figure 19. figure 20 shows the operation of canceling droop effect. a virtual charge current signal is established first and then vid signal plus virtual charge current signal to be generated on the fb pin. hence, an induced charge current signal flows to r1 and is cancelled to reduce droop effect. figure 19. def inition of virtual charge current signal dvid_threshold (set1) dvid_width (set2)
40 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 20. dvid compensation table 6 show the dvid_threshold on the set1 pin with internal 80 a current source and table 7 describes dvid_width settings in set2 pin with external voltage divider. for example, 39.67mv dvid_threshold (sr = 1 1.25mv/ s) / 119mv dvid_threshold (sr = 33.75mv/ s) and 36 s dvid_width are designed (ocp sets as 110% iccmax, rset sets as 133% low frequency ramp / 200% high frequency ramp). according to the table 6 and table 7, the dvid_threshold set voltage should be between 0.4254v to 0.4473v and the dvid_width set voltage should be between 1.051v to 1.073v. please note that a high accuracy resistor is needed for this setting, < 1% error tolerance is recommended. v in gate driver q1 q2 l r esr c o2 cpu c2 charge current induced charge current signal c o1 ai r1 r2 c1 + - ea + - comp ccrcot t on vid transition i droop vid output voltage vin vid virtual charge current slew rate control virtual charge current generator + dvid event set1 i droop has a great cancellation by adding a suitable virtual charge current
41 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 6. set1 pin setting for dvid_threshold set1 r1 r2 v = 80 r1+r2 ? ??? dvid_threshold ocp = %iccmax min typical max unit dvid sr = 11.25mv/ ? s dvid sr = 33.75mv/ ? s 0.000 10.948 21.896 mv 18.33mv 55mv na 25.024 35.973 46.921 mv 110% 50.049 60.997 71.945 mv 120% 75.073 86.022 96.970 mv 130% 100.098 111.046 121.994 mv 140% 125.122 136.070 147.019 mv 150% 150.147 161.095 172.043 mv 160% 175.171 186.119 197.067 mv na 200.196 211.144 222.092 mv 29mv 87mv na 225.220 236.168 247.116 mv 110% 250.244 261.193 272.141 mv 120% 275.269 286.217 297.165 mv 130% 300.293 311.241 322.190 mv 140% 325.318 336.266 347.214 mv 150% 350.342 361.290 372.239 mv 160% 375.367 386.315 397.263 mv na 400.391 411.339 422.287 mv 39.67mv 119mv na 425.415 436.364 447.312 mv 110% 450.440 461.388 472.336 mv 120% 475.464 486.413 497.361 mv 130% 500.489 511.437 522.385 mv 140% 525.513 536.461 547.410 mv 150% 550.538 561.486 572.434 mv 160% 575.562 586.510 597.458 mv na 600.587 611.535 622.483 mv 50.33mv 151mv na 625.611 636.559 647.507 mv 110% 650.635 661.584 672.532 mv 120% 675.660 686.608 697.556 mv 130% 700.684 711.632 722.581 mv 140% 725.709 736.657 747.605 mv 150% 750.733 761.681 772.630 mv 160% 775.758 786.706 797.654 mv na
42 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set1 r1 r2 v = 80 r1+r2 ? ??? dvid_threshold ocp = %iccmax min typical max unit dvid sr = 11.25mv/ ? s dvid sr = 33.75mv/ ? s 800.782 811.730 822.678 mv 61mv 183mv na 825.806 836.755 847.703 mv 110% 850.831 861.779 872.727 mv 120% 875.855 886.804 897.752 mv 130% 900.880 911.828 922.776 mv 140% 925.904 936.852 947.801 mv 150% 950.929 961.877 972.825 mv 160% 975.953 986.901 997.849 mv na 1000.978 1011.926 1022.874 mv 71.67mv 215mv na 1026.002 1036.950 1047.898 mv 110% 1051.026 1061.975 1072.923 mv 120% 1076.051 1086.999 1097.947 mv 130% 1101.075 1112.023 1122.972 mv 140% 1126.100 1137.048 1147.996 mv 150% 1151.124 1162.072 1173.021 mv 160% 1176.149 1187.097 1198.045 mv na 1201.173 1212.121 1223.069 mv 82.33mv 247mv na 1226.197 1237.146 1248.094 mv 110% 1251.222 1262.170 1273.118 mv 120% 1276.246 1287.195 1298.143 mv 130% 1301.271 1312.219 1323.167 mv 140% 1326.295 1337.243 1348.192 mv 150% 1351.320 1362.268 1373.216 mv 160% 1376.344 1387.292 1398.240 mv na 1401.369 1412.317 1423.265 mv 93mv 279mv na 1426.393 1437.341 1448.289 mv 110% 1451.417 1462.366 1473.314 mv 120% 1476.442 1487.390 1498.338 mv 130% 1501.466 1512.414 1523.363 mv 140% 1526.491 1537.439 1548.387 mv 150% 1551.515 1562.463 1573.412 mv 160% 1576.540 1587.488 1598.436 mv na
43 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 7. set2 pin setting for dvid_width set2 r2 v = 3.2v x r1+r2 dvid_width rset %410k rton min typical max unit low f sw ramp high f sw ramp 0.000 10.948 21.896 mv 6 ? s 100% 133% 25.024 35.973 46.921 mv 117% 167% 50.049 60.997 71.945 mv 133% 200% 75.073 86.022 96.970 mv 150% 233% 100.098 111.046 121.994 mv 167% 267% 125.122 136.070 147.019 mv 183% 300% 150.147 161.095 172.043 mv 200% 333% 175.171 186.119 197.067 mv 217% 367% 200.196 211.144 222.092 mv 12 ? s 100% 133% 225.220 236.168 247.116 mv 117% 167% 250.244 261.193 272.141 mv 133% 200% 275.269 286.217 297.165 mv 150% 233% 300.293 311.241 322.190 mv 167% 267% 325.318 336.266 347.214 mv 183% 300% 350.342 361.290 372.239 mv 200% 333% 375.367 386.315 397.263 mv 217% 367% 400.391 411.339 422.287 mv 18 ? s 100% 133% 425.415 436.364 447.312 mv 117% 167% 450.440 461.388 472.336 mv 133% 200% 475.464 486.413 497.361 mv 150% 233% 500.489 511.437 522.385 mv 167% 267% 525.513 536.461 547.410 mv 183% 300% 550.538 561.486 572.434 mv 200% 333% 575.562 586.510 597.458 mv 217% 367% 600.587 611.535 622.483 mv 24 ? s 100% 133% 625.611 636.559 647.507 mv 117% 167% 650.635 661.584 672.532 mv 133% 200% 675.660 686.608 697.556 mv 150% 233% 700.684 711.632 722.581 mv 167% 267% 725.709 736.657 747.605 mv 183% 300% 750.733 761.681 772.630 mv 200% 333% 775.758 786.706 797.654 mv 217% 367% 800.782 811.730 822.678 mv 30 ? s 100% 133% 825.806 836.755 847.703 mv 117% 167% 850.831 861.779 872.727 mv 133% 200% 875.855 886.804 897.752 mv 150% 233% 900.880 911.828 922.776 mv 167% 267% 925.904 936.852 947.801 mv 183% 300% 950.929 961.877 972.825 mv 200% 333% 975.953 986.901 997.849 mv 217% 367%
44 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set2 r2 v = 3.2v x r1+r2 dvid_width rset %130k rton min typical max unit low f sw ramp high f sw ramp 1000.978 1011.926 1022.874 mv 36 ? s 100% 133% 1026.002 1036.950 1047.898 mv 117% 167% 1051.026 1061.975 1072.923 mv 133% 200% 1076.051 1086.999 1097.947 mv 150% 233% 1101.075 1112.023 1122.972 mv 167% 267% 1126.100 1137.048 1147.996 mv 183% 300% 1151.124 1162.072 1173.021 mv 200% 333% 1176.149 1187.097 1198.045 mv 217% 367% 1201.173 1212.121 1223.069 mv 42 ? s 100% 133% 1226.197 1237.146 1248.094 mv 117% 167% 1251.222 1262.170 1273.118 mv 133% 200% 1276.246 1287.195 1298.143 mv 150% 233% 1301.271 1312.219 1323.167 mv 167% 267% 1326.295 1337.243 1348.192 mv 183% 300% 1351.320 1362.268 1373.216 mv 200% 333% 1376.344 1387.292 1398.240 mv 217% 367% 1401.369 1412.317 1423.265 mv 48 ? s 100% 133% 1426.393 1437.341 1448.289 mv 117% 167% 1451.417 1462.366 1473.314 mv 133% 200% 1476.442 1487.390 1498.338 mv 150% 233% 1501.466 1512.414 1523.363 mv 167% 267% 1526.491 1537.439 1548.387 mv 183% 300% 1551.515 1562.463 1573.412 mv 200% 333% 1576.540 1587.488 1598.436 mv 217% 367%
45 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ramp compensation the g-navp tm topology is one type of ripple based control that has fast transient response and can lower bom cost. however, ripple based control usually has poor noise immu nity. RT3606BC provides the ramp compensation to increase noise immunity and reduce jitter at the switching node. figure 21 shows the ram p compensation. noise margin vcomp noise margin imon-vref w/o ramp compensation w/ ramp compensation imon-vref vcomp figure 21. ramp compensation for the RT3606BC, the ramp compensation also needs to be considered during mode transition from ps0/1 to ps2. for achieving smooth mode transition into ps2, a proper ramp compensation design is necessary. since t he ramp compensation needs to be proportional to the on-time, then ramp is set as quick response (qr) mechanism when the transient load step-up becomes quite large, it is difficult for loop response to meet the energy transfer. hence, that output voltage generate undershoot to fail specification. the RT3606BC has quick response (qr) mechanis m being able to improve this issue. it adopts a nonlinear control mechanism which can disable interleaving function and simultaneously turn on all ugate one pulse at instantaneous step-up transient load to restrain the output voltage drooping, figure 22 shows the qr behavior. qr threshold qr width pwm1 pwm2 pwm3 vcore load figure 22. quick response mechanism the output voltage signal behavior needs to be detected so that qr mechanism can be trigged. the output voltage signal is via a remote sense line to connect at vsen pin that is shown in figure 23. the qr mechanism needs to set qr width and qr threshold. both definitions are shown in figure 22. a proper qr mechanism set can meet different applications. set2 can set qr threshold and qr width by internal current source 80 a with mul ti-function pin setting mechanism. figure 23. simplified qr trigger schematic for exam ple, qr threshold 20mv/10mv at ps0/ps1 and 2.22 x ton qr width are set. according to the table 8, the set voltage should be between 0.4505v and 0.4723v. please note that a high accuracy resistor is needed for this setting accuracy, < 1% error tolerance is recommended. in the table 8, there are some ? na ? marks in qrwidth section. it means that use rs should not use it to avoid the possibility of shift digital code due to tolerance concern. s f 133% 400k ? vsen qr pulse generation circuit cmp + - qr_width + - qr_th
46 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 8. set2 pin setting for qr threshold and qr width set2 r1 r2 v = 80 r1+r2 ? ??? qr threshold qr width (%ton) min typical max unit ps0 ps1 0.000 10.948 21.896 mv 15mv 10mv na 25.024 35.973 46.921 mv disable 50.049 60.997 71.945 mv 222% 75.073 86.022 96.970 mv 177.6% 100.098 111.046 121.994 mv 133.2% 125.122 136.070 147.019 mv 88% 150.147 161.095 172.043 mv 44% 175.171 186.119 197.067 mv na 200.196 211.144 222.092 mv 15mv 15mv na 225.220 236.168 247.116 mv disable 250.244 261.193 272.141 mv 222% 275.269 286.217 297.165 mv 177.6% 300.293 311.241 322.190 mv 133.2% 325.318 336.266 347.214 mv 88% 350.342 361.290 372.239 mv 44% 375.367 386.315 397.263 mv na 400.391 411.339 422.287 mv 20mv 10mv na 425.415 436.364 447.312 mv disable 450.440 461.388 472.336 mv 222% 475.464 486.413 497.361 mv 177.6% 500.489 511.437 522.385 mv 133.2% 525.513 536.461 547.410 mv 88% 550.538 561.486 572.434 mv 44% 575.562 586.510 597.458 mv na 600.587 611.535 622.483 mv 20mv 15mv na 625.611 636.559 647.507 mv disable 650.635 661.584 672.532 mv 222% 675.660 686.608 697.556 mv 177.6% 700.684 711.632 722.581 mv 133.2% 725.709 736.657 747.605 mv 88% 750.733 761.681 772.630 mv 44% 775.758 786.706 797.654 mv na
47 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. set2 r1 r2 v = 80 r1+r2 ? ??? qr threshold qr width (%ton) min typical max unit ps0 ps1 800.782 811.730 822.678 mv 25mv 10mv na 825.806 836.755 847.703 mv disable 850.831 861.779 872.727 mv 222% 875.855 886.804 897.752 mv 177.6% 900.880 911.828 922.776 mv 133.2% 925.904 936.852 947.801 mv 88% 950.929 961.877 972.825 mv 44% 975.953 986.901 997.849 mv na 1000.978 1011.926 1022.874 mv 25mv 15mv na 1026.002 1036.950 1047.898 mv disable 1051.026 1061.975 1072.923 mv 222% 1076.051 1086.999 1097.947 mv 177.6% 1101.075 1112.023 1122.972 mv 133.2% 1126.100 1137.048 1147.996 mv 88% 1151.124 1162.072 1173.021 mv 44% 1176.149 1187.097 1198.045 mv na 1201.173 1212.121 1223.069 mv 30mv 10mv na 1226.197 1237.146 1248.094 mv disable 1251.222 1262.170 1273.118 mv 222% 1276.246 1287.195 1298.143 mv 177.6% 1301.271 1312.219 1323.167 mv 133.2% 1326.295 1337.243 1348.192 mv 88% 1351.320 1362.268 1373.216 mv 44% 1376.344 1387.292 1398.240 mv na 1401.369 1412.317 1423.265 mv 30mv 15mv na 1426.393 1437.341 1448.289 mv disable 1451.417 1462.366 1473.314 mv 222% 1476.442 1487.390 1498.338 mv 177.6% 1501.466 1512.414 1523.363 mv 133.2% 1526.491 1537.439 1548.387 mv 88% 1551.515 1562.463 1573.412 mv 44% 1576.540 1587.488 1598.436 mv na
48 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current monitor, imon RT3606BC includes a current monitor (imon) function which can be used to detect over-current protection and the maximum processor current iccmax, and also sets a part of current gain in the load-line setting. it produces an analog voltage proportional to output current between the imon and vref pins. the calculation for imon-vref voltage is shown as below : ??? imon ref eq l1 l2 l3 cs dcr v v = r (i +i +i ) r where i l1 + i l2 + i l3 are output current and the definitions of dcr, r cs and r eq can refer to figure 13. over-current protection the RT3606BC provides over-current protection (ocp) which is set by the set1 pin. the ocp threshold setting can refer to iccmax current in table 5. for example, if iccmax is set as 120a, users can set voltage by using the external voltage divider on the set1 pin as 0.754v typically. if 156a ocp (130% x iccmax) threshold and dvid_th (sr = 11.25mv/ s) = 39.67mv / dvid_th (sr = 33.75mv/ s) = 119mv will be set. according to table 6, the set voltage should be between 0.4755v and 0.4974v. when output current is higher than the ocp threshold, ocp is latched with a 40 s delay to prevent false trigger. besides, the ocp function is masked when dynamic vid transient occurs, and soft-start period. and the ocp function will re-active after 46 s of dvid or soft-start alert is asserted. output over-voltage protection an ovp condition is detected when the vsen pin is 350mv more than vid as vid > 1v. if vid < 1v, the ovp is detected when the vsen pin is 350mv more than 1v. when ovp is detected, the high-side gate voltage ugatex is pulled low and the low-side gate voltage lgatex is pulled high. ovp is latched with a 0.5 s delay to prevent false trigger. besides, the ovp function will be masked during dvid and soft-start period. after 46 s of dvid or soft-start alert is asserted, the ovp function will re-active. negative voltage protection since the ovp latch continuously turns on all low side mosfets of the vr, the vr will suffer negative output voltage. when the vsen detects a voltage below ? 0.07v after triggering ovp, the vr triggers nvp to turn off all low-side mosfets of the vr while the high-side mosfets remains off. after triggering nvp, if the output voltage rises above 0v, the ovp latch restarts to turn on all low-side mosfets. therefore, the output voltage may bounce between 0v and ? 0.07v due to ovp latch and nvp triggering. the nvp function will be active only after ovp is triggered.
49 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v core isen1p isen1n l1 dcr1 r1 c1 + - 680 i l1 i sen1n isen2p isen2n l2 dcr2 r2 c2 + - 680 i l2 i sen2n isen3p isen3n l3 dcr3 r3 c3 + - 680 i l3 i sen3n imon v ref r ntc r eq + - 1/3 + 0.6v comp - + current loop design in details figure 24. current loop structure figure 24 shows the whole current loop structure. the current loop plays an important role in RT3606BC that can decide acll performance, dcll accuracy and iccmax accuracy. for acll performance, the correct compensator design is assumed, if rc network time constant matches inductor time constant l x / dcr x , an expected load transient waveform can be designed. if r x c x network time constant is larger than inductor time constant l x / dcr x , v core waveform has a sluggish droop during load transient. if r x c x network is smaller than inductor time constant l x / dcr x , a worst v core waveform will sag to create an undershooting to fail the specification. figure 25 shows the variety r x c x constant corresponding to the output waveforms.
50 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 25. all kinds of rxcx constants for dcll performance and iccmax accuracy, since the copper wire of inductor has a positive temperature coefficient, when temperature goes high in the heavy load condition, dcr value goes large simultaneously. a resistor network with ntc thermistor compensation connecting between imon and ref pins is necessary, to compensate the positive temperature coefficient of inductor dcr. the design flow is as follows : step1 : given the three system temperature t l , t r and t h , at which are compensated. step2 : three equations can be listed as ?? ?? ?? ? ? ? 4 l li eq l i=1 4 r li eq r i=1 4 h li eq h i=1 dcr (t ) ir (t)=1.6 680 dcr (t ) ir (t)=1.6 680 dcr (t ) ir (t)=1.6 680 where : (1) the relationship between dcr and temperature is as follows : ? ? ?? dcr (t) = dcr (25 c) 1+ 0.00393 (t - 25) (2) r eq (t) is the equivalent resistor of the resistor network with a ntc thermistor ? ? ? ? eq imon1 imon2 imon3 ntc r (t)=r +r //r +r (t) and the relationship between ntc and temperature is as follows : ?? 11 ( - ) t+273 298 ntc ntc r (t)=r (25c)e is in the ntc thermistor datasheet. step3 : three equations and three unknowns, r imon1 , r imon2 and r imon3 can be found out unique solution. ? ? imon2 ntctr imon3 imon1 tr imon2 ntctr imon3 r(r+r) r=k r+r +r 2 r3 ntctl ntctr r3 imon2 ntctl ntctr tl [k +k (r +r ) r= +r r ] ? imon3 imon2 r3 r=r+k where : ? ? th th tr ntcth ntctr kk = rr ? ? tl tl tr ntctl ntctr kk = rr ? ? th tl th tl ntcth ntctl r3 ( / )r r k= 1( / ) ? tl cs (tl) cc-max 1.6 k= gi ? tr cs (tr) cc-max 1.6 k= gi ? th cs (th) cc-max 1.6 k= gi x xx x l rc = dcr ? x xx x l rc < dcr ? x xx x l rc > dcr ? sluggish droop undershoot created in v core v core v imon out ll i x r ? out i ? expected load transient waveform v core v imon out ll i x r ? out i ? v core v imon out ll i x r ? out i ?
51 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. design step : RT3606BC excel based design tool is available. users can contact your richtek representative to get the spreadsheet. three main design procedures for RT3606BC design, first step is initial settings, second step is loop design and the last step is protection settings. the following design example is to explain the RT3606BC design procedure : v core specification input voltage 12v no. of phases 3 iccmax 90a icc-dy 69a icc-tdc 68a load line 2.1m ? fast slew rate 10mv/ ? s max switching frequency 400khz in imvp8 vrtb guideline, the output filter requirements of vrtb specification for desktop platform are : output inductor : 220nh/0.49m output bulk capacitor : 560 f/2.5v/5m (max) 4 to 5pcs output ceramic capacitor : 22 f/0805 (19pcs max in cavity) (1) initial settings : ?? ibias needs to connect a 100k resistor to ground. ?? a voltage divider for setting dvd can choose r dvd_u = 510k and r dvd_l = 125k to set v dvd > 2v, RT3606BC enabled. (2) loop design : ?? on time setting : using the specification, t on is () ton on dac in dac r4.73p1.2 t v 1.2 246n vv ?? ??? ? ?? current sensor adopts lossless rc filter to sense current signal in dcr. for getting an expect load transient waveform, rxcx time constant needs to match lx / dcrx per phase. cx = 0.47 f is set, then the on time setting resistor r ton = 483k x x x l r960 0.47 f dcr ? ??? ? ?? imon resistor network design : t l = 25 c, t r = 50 c an d t h = 100 c are decided, ntc thermistor = 100k @25 c, = 4485 and iccmax = 90a. according to the sub-section ? current loop design in details ? , r imon1 = 10.66k , r imon2 = 16.16k and r imon3 = 1 2.63k can be decided. the r eq (25 c) = 24.91k . ?? load-line design : 2.1m droop is requirement, because r eq (25 c) has decided, the voltage loop av gain is also can be decided by following equation ?? eq cs i ll v 1dcr r 3r a rm ar2 r1 ?? ?? ? where dcr (25 c) = 0.49m , r cs = 680 and r eq (25 c) = 24.91k . hence the a v = r2 / r1 = 2.85 can be obtained. r1 = 10k usually decided, so r2 = 28.5k . ? typical compensator design can use the following equations to design the c1 and c2 values sw 1 c1 470pf r1 f ? ?? ?? out cesr c2 98pf r2 ? ?? for intel platform, in order to induce the band width to enhance transient performa nce to meet intel?s criterion, the compensator of zero can be designed close to 1/10 of switching frequency. ? set1 resistor network design : first the iccmax is design as 90a. next, ocp threshold is designed as 1.5 x iccmax. last, dvid compensation parameters need to be decided. the dvid_th can be calculated as following equation ?? dvid_th out dvid v=llc dt
52 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. where ll is load-line, c out is total output capacitance and dvid/dt is dvid fast slew rate. thus v dvid_th = 50.33mv is needed in this case. by using above information, the two equations can be listed by using multi-function pin setting mechanism r2 0.566 3.2 r1 r2 r1 r2 0.736 80 r1 r2 ? ?? ? ? ?? ? r1 = 52k , r2 = 11.2k . ? set2 resistor network design : ramp = 133% x = 133%, 133% is set. and dvid_width is chosen as 24 sec typical. last, the qr mechanism parameters need to be designed first. init ial qr_th is designed as 25mv and qr_width is designed as 0.44 x t on . by using the information, the two equations can be listed by using multi-function pin setting mechanism r2 0.661 3.2 r1 r2 r1 r2 1.162 80 r1 r2 ? ?? ? ? ?? ? ? ? ? ? tsen ntc (100 c) v 80 a r1// r2 r ? ? ?? ? ? choosing r1 is open and an ntc thermistor r ntc (25 c) = 100k which = 4485. when temperature is 100 c, the r ntc (100!) = 4.85k . then r2 = 8.8k can be calculated. axg vr phase disable (before por) the number of active phases is determined by the internal circuitry that monitors the isenaxn voltages during startup. normally, the vr operates as a 2-phase pwm controller. pulling isena2n to vcc programs a 1-phase operation. before por, vr detects whether the voltages of isena2n is higher than ? vcc-1v ? respectively to decide how many phases should be active. phase selection is only active during por. when por = high, the number of active phases is determined and latched. the unused isenaxp pins are recommended to be connected to vcc and unused pwm pins can be left floating. no load offset (platform) the axg vr features no load offset function which provides the possibility of wide range positive offset of output voltage. users can disable offset function by simply con necting ofsa/psys pin to gnd. figure 26 shows a voltage divider used to set no load offset voltage. no load offset voltage setting is : () ofs_axg ofsa v 0.4 v 1.7 ?? ? the range of v ofs_axg is between ? 500mv and 590mv and the resolution is 10mv. for example, a 100mv no load offset requirement, v ofsa needs to be set as 1.95v. dac + + + svid offset register svid vid register pin offset register adc v cc r1 r2 ofsa/psys vid_ref figure 26. no load offset circuit 400k 400k r 1= 70.3k , r2 = 18.2k . (1) protection settings : ? ovp protections : when vsen pin voltage is 350mv more than vid, the ovp will be latched. ? tsen and vr_hot design : using the following equation to calculate related resistances for vr_hot setting.
53 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. switching frequency setting as mention in switching frequency setting section of core vr, connect a resistor r tona between input terminal and tonseta pin to set the on-time width. tona ona dac in dac tona dac ona dac in dac r4.793p1.2 t(v1.2) vv r4.793pv t(v1.2) vv ?? ?? ? ?? ?? ? for better efficiency of the given load range, the maximum switching frequency is suggested to be : ?? swa(max) on_ls,max ll ls on_ls,max on_hs,max on_ls,max in(max) ona d ona,var d ls hs ls f r icctdc vid1 dcr n r nn rr r icctdc icctdc vtttt nn n nn ? ?? ??? ?? ?? ?? ?? ?? ?? ?? ? ??? ?? ? ?? ?? ?? ?? ?? ?? ?? where f sw(max) is the maximum switching frequency, vid1 is the typical vid of application, v in (max) is the maximum application input voltage, icctdc is the thermal design current of application, n is the phase number. the r on_hs,max is the maximum equivalent high-side r ds(on) , and n hs is the number of high-side mosfets; r on_ls,max is the maximum equivalent low-side r ds(on) , and n ls is the number of low-side mosfets. t d is the summation of the high-side mosfet delay time and the rising time, t on,var is the t on variation value. dcr is the inductor dcr, and r ll is the loadline setting. in addition, richtek provides a microsoft excel-based spreadsheet to help design the r ton for RT3606BC. when load increases, on-time keeps constant. the off- time width will be reduced so that loading can load more power from input terminal to regulate output voltage. hence the loading current usually increases in case the switching frequency also increases. higher switching frequency operation can reduce power components' size and pcb space, trading off the whole efficiency since switching related switching related loss increases, vice versa. per phase current sense in the RT3606BC, the current signal is used for load-line setting and over-current protection (ocp). the inductor current sense method adopts the lossless c urrent sensing for allowing high efficiency as illustrated in the figure 27. when inductance and dcr time constant is equal to r ax c ax filter network time constant, a voltage i lax x dcr will drop on c ax to generate inductor current signal. according to the figure 27, the isenaxn is as follows : lax csax idcr isenaxn r ? ? where l ax / dcr = r ax c ax is held. the method can get high efficiency performance, but dcr value will be drifted by temperature, a ntc resistor should add in the resistor network in the imona pin to achieve dcr thermal compen sation. in RT3606BC design, the resistance of r csax is restricted to 680 ; moreover, the error of r csax is recommended to be 1% or smaller. isenaxp isenaxn l ax dcr r ax c ax v axg + - r csax i lax i senaxn figure 27. lossless current sense method total current sense as presented in total current sense section of axg vr, figure 28 shows the total current sense method which connects the resistor network between imona and vref pins to set a part of current loop gain for load-line (droop) setting and set accurate over current protection. imona ref eqa la1 la2 cs dcr vv r(ii) r ????? r eqa includes a ntc resistor to compensate dcr thermal drifting for high accuracy load-line (droop).
54 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 28. total current sense method load-line (droop) setting the g-navp tm topology can set load-line (droop) via the current loop and the voltage loop, the load-line is a slope between load current i cca and output voltage v axg as shown figure 29. figure 30 shows the voltage control and current loop. by using the both loops, the load-line (droop) can be set easily. the load-line set equat ion is : ?? eqa cs i lla v 1 dcr r 3r a rm ara2 ra1 ?? ?? ? i cca v axg load line slope = -r lla r lla x i cca figure 29. load-line (droop) + - ra2 ra1 vid c r la dcr i l1.2 + - isena[1:2]n isena[1:2]p r cs i sena1n + i sena2n + - 1/3 + - voltage loop ton generator r eqa imona r ntc v ref v axg figure 30. voltage loop and current loop compensator design the compensator of RT3606BC doesn't need a complex type ii or type iii compensator to optimize control loop performance. it can adopt a simple type i compensator (one pole, one zero) in g-navp tm topology to achieve constant output impedance design for intel imvp8 acll specification. the one pole one zero compensator is shown as figure 31, the transfer function of compensator should be design as following transfer function to achieve constant output impedance, i.e. z o(s) = load-line slope in the entire frequency range 1 1 swa i con lla esra s f a g(s) rs ? ? ? ? ? ? where a i is current loop gain, r lla is load line for axg vr, f swa is switching frequency for axg vr and esra is a pole that should be located at 1 / (c outa x esr). then the ca1 and ca2 should be designed as follows : swa 1 ca1 ra1 f ? ? ?? outa c esr ca2 ra2 ? ? + - ra2 ra1 vid ca2 ca1 figure 31. type i compensator v axg isena1p isena1n l dcr r c + - r csa i la1 i sena1n isena2p isena2n l dcr r c + - r csa i la2 i sena2n v ref imona r ntc r eqa
55 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. differential remote sense setting the vr provides differential remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu c ontains on-die sense pins, v ccaxg_sense and v ssaxg_sense . connect rgnda to v ssaxg_sense and connect fba to v ccaxg_sense with a resistor to build the negative input path of the error amplifier as shown in figure 32. the v dac and the precision voltage reference are referred to rgnda for accurate remote sensing. cpu v ccaxg_sense - + fba rgnda ea - + vid r1 cpu v ssaxg_sense r2 v outa c outa figure 32. remote sensing circuit maximum processor current setting, iccmaxa the maximum processor current iccmaxa can be set by the seta1 pin. iccmaxa register is set by an external voltage divider with the multi-function mechanism. table 9 shows the iccmaxa setting on the seta1 pin. for example, iccmaxa = 40a, the viccmaxa needs to set as 0.253 typical. additionally, v imona ? v ref needs to be set as 1.6v at iccmaxa when the maximum phase >1. as in 1-phase application, the v imona ? v ref needs to be set as 0.4v at iccmaxa. the iccmaxa alert signal will be pulled to low level. if v imona ? v ref = 1.6v (for maximum phase >1) or v imona ? v ref = 0.4v (for 1-phase application)
56 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 9. seta1 pin setting for iccmaxa seta1 r2 v3.2v r1 r2 ?? ? iccmaxa unit min typical max unit 0.000 3.128 6.256 mv 0 a 12.512 15.640 18.768 mv 2 a 25.024 28.152 31.281 mv 4 a 37.537 40.665 43.793 mv 6 a 50.049 53.177 56.305 mv 8 a 62.561 65.689 68.817 mv 10 a 75.073 78.201 81.329 mv 12 a 87.586 90.714 93.842 mv 14 a 100.098 103.226 106.354 mv 16 a 112.610 115.738 118.866 mv 18 a 125.122 128.250 131.378 mv 20 a 137.634 140.762 143.891 mv 22 a 150.147 153.275 156.403 mv 24 a 162.659 165.787 168.915 mv 26 a 175.171 178.299 181.427 mv 28 a 187.683 190.811 193.939 mv 30 a 200.196 203.324 206.452 mv 32 a 212.708 215.836 218.964 mv 34 a 225.220 228.348 231.476 mv 36 a 237.732 240.860 243.988 mv 38 a 250.244 253.372 256.500 mv 40 a 262.757 265.885 269.013 mv 42 a 275.269 278.397 281.525 mv 44 a 287.781 290.909 294.037 mv 46 a 300.293 303.421 306.549 mv 48 a 312.805 315.934 319.062 mv 50 a 325.318 328.446 331.574 mv 52 a 337.830 340.958 344.086 mv 54 a 350.342 353.470 356.598 mv 56 a 362.854 365.982 369.110 mv 58 a 375.367 378.495 381.623 mv 60 a 387.879 391.007 394.135 mv 62 a 400.391 403.519 406.647 mv 64 a 412.903 416.031 419.159 mv 66 a
57 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta1 r2 v3.2v r1 r2 ?? ? iccmaxa unit min typical max unit 425.415 428.543 431.672 mv 68 a 437.928 441.056 444.184 mv 70 a 450.440 453.568 456.696 mv 72 a 462.952 466.080 469.208 mv 74 a 475.464 478.592 481.720 mv 76 a 487.977 491.105 494.233 mv 78 a 500.489 503.617 506.745 mv 80 a 513.001 516.129 519.257 mv 82 a 525.513 528.641 531.769 mv 84 a 538.025 541.153 544.282 mv 86 a 550.538 553.666 556.794 mv 88 a 563.050 566.178 569.306 mv 90 a 575.562 578.690 581.818 mv 92 a 588.074 591.202 594.330 mv 94 a 600.587 603.715 606.843 mv 96 a 613.099 616.227 619.355 mv 98 a 625.611 628.739 631.867 mv 100 a 638.123 641.251 644.379 mv 102 a 650.635 653.763 656.891 mv 104 a 663.148 666.276 669.404 mv 106 a 675.660 678.788 681.916 mv 108 a 688.172 691.300 694.428 mv 110 a 700.684 703.812 706.940 mv 112 a 713.196 716.325 719.453 mv 114 a 725.709 728.837 731.965 mv 116 a 738.221 741.349 744.477 mv 118 a 750.733 753.861 756.989 mv 120 a 763.245 766.373 769.501 mv 122 a 775.758 778.886 782.014 mv 124 a 788.270 791.398 794.526 mv 126 a 800.782 803.910 807.038 mv 128 a 813.294 816.422 819.550 mv 130 a 825.806 828.935 832.063 mv 132 a 838.319 841.447 844.575 mv 134 a 850.831 853.959 857.087 mv 136 a
58 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta1 r2 v3.2v r1 r2 ?? ? iccmaxa unit min typical max unit 863.343 866.471 869.599 mv 138 a 875.855 878.983 882.111 mv 140 a 888.368 891.496 894.624 mv 142 a 900.880 904.008 907.136 mv 144 a 913.392 916.520 919.648 mv 146 a 925.904 929.032 932.160 mv 148 a 938.416 941.544 944.673 mv 150 a 950.929 954.057 957.185 mv 152 a 963.441 966.569 969.697 mv 154 a 975.953 979.081 982.209 mv 156 a 988.465 991.593 994.721 mv 158 a 1000.978 1004.106 1007.234 mv 160 a 1013.490 1016.618 1019.746 mv 162 a 1026.002 1029.130 1032.258 mv 164 a 1038.514 1041.642 1044.770 mv 166 a 1051.026 1054.154 1057.283 mv 168 a 1063.539 1066.667 1069.795 mv 170 a 1076.051 1079.179 1082.307 mv 172 a 1088.563 1091.691 1094.819 mv 174 a 1101.075 1104.203 1107.331 mv 176 a 1113.587 1116.716 1119.844 mv 178 a 1126.100 1129.228 1132.356 mv 180 a 1138.612 1141.740 1144.868 mv 182 a 1151.124 1154.252 1157.380 mv 184 a 1163.636 1166.764 1169.892 mv 186 a 1176.149 1179.277 1182.405 mv 188 a 1188.661 1191.789 1194.917 mv 190 a 1201.173 1204.301 1207.429 mv 192 a 1213.685 1216.813 1219.941 mv 194 a 1226.197 1229.326 1232.454 mv 196 a 1238.710 1241.838 1244.966 mv 198 a 1251.222 1254.350 1257.478 mv 200 a 1263.734 1266.862 1269.990 mv 202 a 1276.246 1279.374 1282.502 mv 204 a 1288.759 1291.887 1295.015 mv 206 a
59 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta1 r2 v3.2v r1 r2 ?? ? iccmaxa unit min typical max unit 1301.271 1304.399 1307.527 mv 208 a 1313.783 1316.911 1320.039 mv 210 a 1326.295 1329.423 1332.551 mv 212 a 1338.807 1341.935 1345.064 mv 214 a 1351.320 1354.448 1357.576 mv 216 a 1363.832 1366.960 1370.088 mv 218 a 1376.344 1379.472 1382.600 mv 220 a 1388.856 1391.984 1395.112 mv 222 a 1401.369 1404.497 1407.625 mv 224 a 1413.881 1417.009 1420.137 mv 226 a 1426.393 1429.521 1432.649 mv 228 a 1438.905 1442.033 1445.161 mv 230 a 1451.417 1454.545 1457.674 mv 232 a 1463.930 1467.058 1470.186 mv 234 a 1476.442 1479.570 1482.698 mv 236 a 1488.954 1492.082 1495.210 mv 238 a 1501.466 1504.594 1507.722 mv 240 a 1513.978 1517.107 1520.235 mv 242 a 1526.491 1529.619 1532.747 mv 244 a 1539.003 1542.131 1545.259 mv 246 a 1551.515 1554.643 1557.771 mv 248 a 1564.027 1567.155 1570.283 mv 250 a 1576.540 1579.668 1582.796 mv 252 a 1589.052 1592.180 1595.308 mv 254 a
60 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dynamic vid (dvid) compensation for axg vr as mention in dvid compensation section of core vr, the RT3606BC also provide a dvid compensation function for axg vr. a virtual charge current signal can be established by seta1 and seta2 pins to cancel the real induced charge current signal. table 10 show the dvid_threshold in seta1 pin with internal 80 a current source and table 11 describes dvid_width settings on seta2 pin with external voltage divider. for example, 39.67mv dvid_threshold (sr = 11.25mv/ s) / 119mv dvid_threshold (sr = 33.75mv/ s) and 36 s dvid_width are designed (ocpa sets as 110% iccmaxa, rseta sets as 133% low frequency ramp / 200% high frequency ramp). according to the table 10 and table 11, the dvid_threshold set voltage should be between 0.4254v to 0.4473v and the dvid_width set voltage should be between 1.051v to 1.073v. please note that a high accuracy resistor is needed for this setting, < 1% error tolerance is recommended. table 10. seta1 pin setting for dvid_threshold seta1 r1 r2 v = 80 r1+r2 ? ??? dvid_threshold ocp = %iccmax min typical max unit dvid sr = 11.25mv/ ? s dvid sr = 33.75mv/ ? s 0.000 10.948 21.896 mv 18.33mv 55mv na 25.024 35.973 46.921 mv 110% 50.049 60.997 71.945 mv 120% 75.073 86.022 96.970 mv 130% 100.098 111.046 121.994 mv 140% 125.122 136.070 147.019 mv 150% 150.147 161.095 172.043 mv 160% 175.171 186.119 197.067 mv na 200.196 211.144 222.092 mv 29mv 87mv na 225.220 236.168 247.116 mv 110% 250.244 261.193 272.141 mv 120% 275.269 286.217 297.165 mv 130% 300.293 311.241 322.190 mv 140% 325.318 336.266 347.214 mv 150% 350.342 361.290 372.239 mv 160% 375.367 386.315 397.263 mv na 400.391 411.339 422.287 mv 39.67mv 119mv na 425.415 436.364 447.312 mv 110% 450.440 461.388 472.336 mv 120% 475.464 486.413 497.361 mv 130% 500.489 511.437 522.385 mv 140% 525.513 536.461 547.410 mv 150% 550.538 561.486 572.434 mv 160% 575.562 586.510 597.458 mv na
61 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta1 r1 r2 v = 80 r1+r2 ? ??? dvid_threshold ocp = %iccmax min typical max unit dvid sr = 11.25mv/ ? s dvid sr = 33.75mv/ ? s 600.587 611.535 622.483 mv 50.33mv 151mv na 625.611 636.559 647.507 mv 110% 650.635 661.584 672.532 mv 120% 675.660 686.608 697.556 mv 130% 700.684 711.632 722.581 mv 140% 725.709 736.657 747.605 mv 150% 750.733 761.681 772.630 mv 160% 775.758 786.706 797.654 mv na 800.782 811.730 822.678 mv 61mv 183mv na 825.806 836.755 847.703 mv 110% 850.831 861.779 872.727 mv 120% 875.855 886.804 897.752 mv 130% 900.880 911.828 922.776 mv 140% 925.904 936.852 947.801 mv 150% 950.929 961.877 972.825 mv 160% 975.953 986.901 997.849 mv na 1000.978 1011.926 1022.874 mv 71.67mv 215mv na 1026.002 1036.950 1047.898 mv 110% 1051.026 1061.975 1072.923 mv 120% 1076.051 1086.999 1097.947 mv 130% 1101.075 1112.023 1122.972 mv 140% 1126.100 1137.048 1147.996 mv 150% 1151.124 1162.072 1173.021 mv 160% 1176.149 1187.097 1198.045 mv na 1201.173 1212.121 1223.069 mv 82.33mv 247mv na 1226.197 1237.146 1248.094 mv 110% 1251.222 1262.170 1273.118 mv 120% 1276.246 1287.195 1298.143 mv 130% 1301.271 1312.219 1323.167 mv 140% 1326.295 1337.243 1348.192 mv 150% 1351.320 1362.268 1373.216 mv 160% 1376.344 1387.292 1398.240 mv na 1401.369 1412.317 1423.265 mv 93mv 279mv na 1426.393 1437.341 1448.289 mv 110% 1451.417 1462.366 1473.314 mv 120% 1476.442 1487.390 1498.338 mv 130% 1501.466 1512.414 1523.363 mv 140% 1526.491 1537.439 1548.387 mv 150% 1551.515 1562.463 1573.412 mv 160% 1576.540 1587.488 1598.436 mv na
62 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 11. seta2 pin setting for dvid_width seta2 r2 v = 3.2v x r1+r2 dvid_width rset %410k rton min typical max unit low f sw ramp high f sw ramp 0.000 10.948 21.896 mv 6 ? s 100% 133% 25.024 35.973 46.921 mv 117% 167% 50.049 60.997 71.945 mv 133% 200% 75.073 86.022 96.970 mv 150% 233% 100.098 111.046 121.994 mv 167% 267% 125.122 136.070 147.019 mv 183% 300% 150.147 161.095 172.043 mv 200% 333% 175.171 186.119 197.067 mv 217% 367% 200.196 211.144 222.092 mv 12 ? s 100% 133% 225.220 236.168 247.116 mv 117% 167% 250.244 261.193 272.141 mv 133% 200% 275.269 286.217 297.165 mv 150% 233% 300.293 311.241 322.190 mv 167% 267% 325.318 336.266 347.214 mv 183% 300% 350.342 361.290 372.239 mv 200% 333% 375.367 386.315 397.263 mv 217% 367% 400.391 411.339 422.287 mv 18 ? s 100% 133% 425.415 436.364 447.312 mv 117% 167% 450.440 461.388 472.336 mv 133% 200% 475.464 486.413 497.361 mv 150% 233% 500.489 511.437 522.385 mv 167% 267% 525.513 536.461 547.410 mv 183% 300% 550.538 561.486 572.434 mv 200% 333% 575.562 586.510 597.458 mv 217% 367% 600.587 611.535 622.483 mv 24 ? s 100% 133% 625.611 636.559 647.507 mv 117% 167% 650.635 661.584 672.532 mv 133% 200% 675.660 686.608 697.556 mv 150% 233% 700.684 711.632 722.581 mv 167% 267% 725.709 736.657 747.605 mv 183% 300% 750.733 761.681 772.630 mv 200% 333% 775.758 786.706 797.654 mv 217% 367%
63 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta2 r2 v = 3.2v x r1+r2 dvid_width rset %410k rton min typical max unit low f sw ramp high f sw ramp 800.782 811.730 822.678 mv 30 ? s 100% 133% 825.806 836.755 847.703 mv 117% 167% 850.831 861.779 872.727 mv 133% 200% 875.855 886.804 897.752 mv 150% 233% 900.880 911.828 922.776 mv 167% 267% 925.904 936.852 947.801 mv 183% 300% 950.929 961.877 972.825 mv 200% 333% 975.953 986.901 997.849 mv 217% 367% 1000.978 1011.926 1022.874 mv 36 ? s 100% 133% 1026.002 1036.950 1047.898 mv 117% 167% 1051.026 1061.975 1072.923 mv 133% 200% 1076.051 1086.999 1097.947 mv 150% 233% 1101.075 1112.023 1122.972 mv 167% 267% 1126.100 1137.048 1147.996 mv 183% 300% 1151.124 1162.072 1173.021 mv 200% 333% 1176.149 1187.097 1198.045 mv 217% 367% 1201.173 1212.121 1223.069 mv 42 ? s 100% 133% 1226.197 1237.146 1248.094 mv 117% 167% 1251.222 1262.170 1273.118 mv 133% 200% 1276.246 1287.195 1298.143 mv 150% 233% 1301.271 1312.219 1323.167 mv 167% 267% 1326.295 1337.243 1348.192 mv 183% 300% 1351.320 1362.268 1373.216 mv 200% 333% 1376.344 1387.292 1398.240 mv 217% 367% 1401.369 1412.317 1423.265 mv 48 ? s 100% 133% 1426.393 1437.341 1448.289 mv 117% 167% 1451.417 1462.366 1473.314 mv 133% 200% 1476.442 1487.390 1498.338 mv 150% 233% 1501.466 1512.414 1523.363 mv 167% 267% 1526.491 1537.439 1548.387 mv 183% 300% 1551.515 1562.463 1573.412 mv 200% 333% 1576.540 1587.488 1598.436 mv 217% 367%
64 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ramp compensation g-navp tm topology is one type of ripple based control that has fast tran sient response and can lower bom cost. however, ripple based control usually has poor noise immunity. the RT3606BC provides the ramp compensation in axg vr to increase noise immunity and reduce jitter at the switching node. figure 33 shows the ramp compensation. noise margin vcompa noise margin imona-vref w/o ramp compensation w/ ramp compensation imona-vref vcompa figure 33. ramp compensation for the RT3606BC, the ramp compensation also needs to be considered during mode transition from ps0/1 to ps2. for achieving smooth mode transition into ps2, a proper ramp compensation design is necessary. since the ramp compensation needs to be proportional to the on-time, then ramp is set as quick response (qr) mechanism as presented in qr mechanism section of core vr, RT3606BC also supports qr function in axg vr. the output voltage signal behavior needs to be detected so that qr me chanism can be trigged. the output voltage signal is via a remote sense line to connect at vsena pin that is shown in figure 34. the qr mechanism needs to set qr width and qr threshold. both definitions are shown in figure 22. a proper qr mechanism set can meet different applications. seta2 can set qr threshold and qr width by internal current source 80 a with multi- function pin setting mechanism. figure 34. simplified qr trigger schematic f or example, qr threshold 20mv/10mv at ps0/ps1 and 2.22 x ton qr width are set. according to the table 12, the set voltage should be between 0.4504v and 0.4723v. please note that a high accuracy resistor is needed for this setting accuracy, < 1% error tolerance is recommended. in the table 12, there are some ? na ? marks in qrwidth section. it means that user should not use it to avoid the possibility of shift digital code due to tolerance concern. s f 133% 400k ? vsena qr pulse generation circuit cmp + - qr_width + - qr_th
65 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 12. seta2 pin setting for qr threshold and qr width seta2 r1 r2 v = 80 r1+r2 ? ??? qr threshold qr width (%ton) min typical max unit ps0 ps1 0.000 10.948 21.896 mv 15mv 10mv na 25.024 35.973 46.921 mv disable 50.049 60.997 71.945 mv 222% 75.073 86.022 96.970 mv 177.6% 100.098 111.046 121.994 mv 133.2% 125.122 136.070 147.019 mv 88% 150.147 161.095 172.043 mv 44% 175.171 186.119 197.067 mv na 200.196 211.144 222.092 mv 15mv 15mv na 225.220 236.168 247.116 mv disable 250.244 261.193 272.141 mv 222% 275.269 286.217 297.165 mv 177.6% 300.293 311.241 322.190 mv 133.2% 325.318 336.266 347.214 mv 88% 350.342 361.290 372.239 mv 44% 375.367 386.315 397.263 mv na 400.391 411.339 422.287 mv 20mv 10mv na 425.415 436.364 447.312 mv disable 450.440 461.388 472.336 mv 222% 475.464 486.413 497.361 mv 177.6% 500.489 511.437 522.385 mv 133.2% 525.513 536.461 547.410 mv 88% 550.538 561.486 572.434 mv 44% 575.562 586.510 597.458 mv na 600.587 611.535 622.483 mv 20mv 15mv na 625.611 636.559 647.507 mv disable 650.635 661.584 672.532 mv 222% 675.660 686.608 697.556 mv 177.6% 700.684 711.632 722.581 mv 133.2% 725.709 736.657 747.605 mv 88% 750.733 761.681 772.630 mv 44% 775.758 786.706 797.654 mv na
66 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. seta2 r1 r2 v = 80 r1+r2 ? ??? qr threshold qr width (%ton) min typical max unit ps0 ps1 800.782 811.730 822.678 mv 25mv 10mv na 825.806 836.755 847.703 mv disable 850.831 861.779 872.727 mv 222% 875.855 886.804 897.752 mv 177.6% 900.880 911.828 922.776 mv 133.2% 925.904 936.852 947.801 mv 88% 950.929 961.877 972.825 mv 44% 975.953 986.901 997.849 mv na 1000.978 1011.926 1022.874 mv 25mv 15mv na 1026.002 1036.950 1047.898 mv disable 1051.026 1061.975 1072.923 mv 222% 1076.051 1086.999 1097.947 mv 177.6% 1101.075 1112.023 1122.972 mv 133.2% 1126.100 1137.048 1147.996 mv 88% 1151.124 1162.072 1173.021 mv 44% 1176.149 1187.097 1198.045 mv na 1201.173 1212.121 1223.069 mv 30mv 10mv na 1226.197 1237.146 1248.094 mv disable 1251.222 1262.170 1273.118 mv 222% 1276.246 1287.195 1298.143 mv 177.6% 1301.271 1312.219 1323.167 mv 133.2% 1326.295 1337.243 1348.192 mv 88% 1351.320 1362.268 1373.216 mv 44% 1376.344 1387.292 1398.240 mv na 1401.369 1412.317 1423.265 mv 30mv 15mv na 1426.393 1437.341 1448.289 mv disable 1451.417 1462.366 1473.314 mv 222% 1476.442 1487.390 1498.338 mv 177.6% 1501.466 1512.414 1523.363 mv 133.2% 1526.491 1537.439 1548.387 mv 88% 1551.515 1562.463 1573.412 mv 44% 1576.540 1587.488 1598.436 mv na
67 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current monitor, imona RT3606BC includes a current monitor (imona) function which can be used to detect over current protection and the maximum processor current iccmaxa, and also sets a part of current gain in the load-line setting. it produces an analog voltage proportional to output current between the imona and vref pins. the calculation for imona-vref voltage is shown as below : imona ref eqa la1 la2 csa dcr vv r(ii) r ?? ??? where i la1 + i la2 are output current and the definitions of dcr, r csa and r eqa can refer to figure 28. over current protection RT3606BC provides the over current protection (ocp) which is set by the seta1 pin in axg vr. the ocp threshold setting can refer to iccmaxa current in the table 9. for example, if iccmaxa is set as 120a, user can set voltage by using the external voltage divider on seta1 pin as 0.759v typically. if 156a ocp (130% x iccmax) threshold and dvid_th (sr = 11.25mv/ s) = 39.67mv / dvid_th (sr = 33.75mv/ s) = 119mv will be set. according to table 10, the set voltage should be between 0.4755v and 0.4974v. when output current is higher than the ocp threshold, ocp is latched with a 40 s delay to prevent false trigger. besides, the ocp function is masked when dynamic vid transient occurs, and soft-start period. and the ocp function will re-active after 46 s of dvid or soft-start alert is asserted. output over-voltage protection an ovp condition is detected when the vsena pin is 150mv more than vid. as vid > 1v. if vid < 1v, the ovp is detected when the vsen pin is 350mv more than 1v. when ovp is detected, the high-side gate voltage ugateax is pulled low and the low-side gate voltage lgateax is pulled high, ovp is latched with a 0.5 s delay to prevent false trigger. besides, the ovp function will be masked during dvid and soft-start period. after 46 s of dvid or soft-start alert is asserted, the ovp function will re-active. negative voltage protection since the ovp latch continuously turns on all low-side mosfets of the vr, the vr will suffer negative output voltage. when the vsena detects a voltage below ? 0.07v after triggering ovp, the vr triggers nvp to turn off all low-side mosfets of the vr while the high-side mosfets remain off. after triggering nvp, if the output voltage rises above 0v, the ovp latch restarts to turn on all low-side mosfets. therefore, the output voltage may bounce between 0v and ? 0.07v due to ovp latch and nvp triggering. the nvp function will be active only after ovp is triggered. current loop design in details figure 35 shows the whole current loop structure. the current loop plays an important role in the RT3606BC that can decide acll performance, dcll accuracy and iccmaxa accuracy. for acll performance, the correct compensator design is assumed, if rc network time constant matches inductor time constant l ax / dcr x , an expected load transient wa veform can be designed. if r x c x network time constant is larger than inductor time constant l ax / dcr x , v axg waveform has a sluggish droop during load transient. if r x c x network is smaller than inductor time constant l ax /dcr x , a worst v axg waveform will sag to create an undershooting to fail the specification. for dcll performance and iccmaxa accuracy, since the copper wire of inductor has a positive temperature coefficient, when temperature goes high in the heavy load condition, dcr value goes large simultaneously. a resistor network with ntc thermistor compensation connecting between the imona to ref pins is necessary, to compensate the positive temperature coefficient of inductor dcr. the design flow is as presented in current loop design in details of core vr.
68 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 35. current loop structure design step the RT3606BC excel based design tool is available. users can contact your richtek representative to get the spreadsheet. three main design procedures for RT3606BC design, first step is initial settings, second step is loop design and the last step is protection settings. the following design example is to explain RT3606BC design procedure : v axg specification input voltage 12v no. of phases 2 vboot 0.9v iccmax 76a icc-dy 42a icc-tdc 45a load line 3.1m ? fast slew rate 10mv/ ? s max switching frequency 400khz v axg isena1p isena1n la1 dcr1 r1 c1 + - 680 i la1 i sena1n isena2p isena2n la2 dcr2 r2 c2 + - 680 i la2 i sena2n imona v ref r ntc r eqa + - 1/3 + 0.6v compa - + system input power monitor, psys the RT3606BC provides psys function to monitor total platform system power, and the obtained information will be provided directly to the cpu via the svid interface. the psys function can be enabled/disabled by the set3 pin. the psys function can be described as in figure36. when psys voltage v psys = 3.2v, the RT3606BC will generate an 8-bit code, ff, for 100% pmax, which will be stored in the 1bh register. to choose the resistor value r, for example, if the maximum current from the psys ? meter ? i = 320 a in conjunction with v psys = 3.2v for 100% pmax, r = v psys / i =10k can be obtained. the resistor must be as close to the RT3606BC as. figure 36. psys function block diagram input power source psys "meter" RT3606BC psys cpu i svid r current mode analog signal (indicates system total power) v psys
69 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. in imvp8 vrtb guideline, the output filter requirements of vrtb specification for desktop platform are : output inductor : 22 0nh/0.49m output bulk capacitor : 470 f/2.5v/7m (max) 4 to 5pcs output ceramic capacitor : 22 f/0805 (14pcs max in cavity) (1) initial settings : RT3606BC initial voltage is 0.9v (2) loop design : on time setting : using the specification, t ona is ( ona ona dac in dac t4.73p1.2 t = v < 1.2) = 204n v-v ?? the on time setting resi stor r tona = 400k ? current sensor adopts lossless rc filter to sense current signal in dcr. for getting an expect load transient waveform, rxcx time constant needs to match lx / dcrx per phase. cx = 0.47 f is set, then x x x l r 780 0.47 f dcr ? ??? ? ? imona resistor network design : t l = 25 c, t r = 50 c and t h = 100 c are decide d, ntc thermistor = 100k @25 c, = 4485 and iccmaxa = 76a. according to the sub-section ? current loop design in details ? , r imona1 = 10.6k , r imona2 = 15.05k and r imona3 = 11.46k can be decided. the r eqa (25 c) = 23.86k . ? load-line design : 2.1m droop is requirement, becaus e r eqa (25 c) has decided, the voltage loop av gain is also can be decided by following equation ?? eqa csa i lla v 1dcr r 3r a rm ar2 r1 ?? ?? ? where dcr (25 c) = 0.6m , r cs = 680 and r eqa (25 c) = 23.86k . hence the a v = r2 / r1 = 2.26 can be obtained. r = 10k usually is decided, so r2 = 22.6k . ? typical compensator design can use the following equations to design the c1 and c2 values swa 1 c2 87pf r1 f ? ?? ?? out c esr c2 115pf r2 ? ?? for intel platform, in order to induce the band width to enhance transient performa nce to meet intel?s criterion, the compensator of zero can be designed close to 1/10 of switching frequency. ? seta1 resistor network design : first the iccmax is design as 76a. next, ocp threshold is designed as 1.5 x iccmax. last, dvid compensation parameters need to be decided. the dvid_th can be calculated as following equation dvid_th out dvid v = llc dt ?? where ll is load line, c out is total output capacitance and dvid/dt is dvid fast slew rate. thus v dvid_th = 39.67mv is needed in this case. by using above information, the two equations can be listed by using multi-function pin setting mechanism r2 0.479 3.2 r1 r2 r1 r2 0.536 80 r1 r2 ? ?? ? ? ?? ? r1 = 44.84k , r2 = 7.89k . ? seta2 resistor network design : ramp = 133% x = 133%, 133% is set. and dvid_width is chosen as 24 sec typical. last, the qr mechanism parameters need to be designed first. initial qr_th is designed as 20mv and qr_width is designed as 0.44 x t on . by using the information, the two equations can be listed by using multi-funct ion pin setting mechanism r2 0.661 3.2 r1 r2 r1 r2 0.761 80 r1 r2 ? ?? ? ? ?? ? r1 = 46.05k , r2 = 12k . 400k 400k
70 RT3606BC www.richtek.com ds3606bc-04 june 2016 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. (3) protection settings : ? ovp protections : when the vsena pin voltage is 350mv more than vid, the ovp will be latched. when vsena pin voltage is 350mv less than vid, the uvp will be latched. ? tsen and vr_hot design : using the following equation to calculate related resistances for vr_hot setting. ? ? ? ? tsena antc (100 c) v80ara1//ra2r ? ? ?? ? (4) addressing settings : ? set3 resistor network design : based on table13 information, the two equations can be listed as following r2 0.060 3.2v r1 r2 r1 r2 0.261 80 r1 r2 ?? ? ? ??? ? r1 = 171.3k , r2 = 3.32k . function1 main address:00 auxiliary address:01 main and auxiliary rail disable zero load anti-oversh oot function disable anti-overshoot pwm behavior is high to tri stage. ai gain is 1. function2 psys function disable select low frequency ramp table dvid slew rate is 11.25mv/ ? s enable dvid compensation function when 1 phase application, ramp increase. table 13. set3 design information thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-60l 7x7 package, the thermal resistance, ja , is 25.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (25.5 c/w) = 3.92w for wqfn-60l 7x7 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 37 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 37. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
71 RT3606BC ds3606bc-04 june 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension w-type 60l qfn 7x7 package min. max. min. max. a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 6.900 7.100 0.272 0.280 d2 5.650 5.750 0.222 0.226 e 6.900 7.100 0.272 0.280 e2 5.650 5.750 0.222 0.226 e l 0.350 0.450 0.014 0.018 h 0.250 0.350 0.010 0.014 symbol dimensions in millimeters dimensions in inches 0.400 0.016 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
72 RT3606BC www.richtek.com ds3606bc-04 june 2016 richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries.

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